static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
struct northbridge_intel_gm45_config *conf = dev->chip_info;
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
}
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
u32 physbase;
struct resource *lfb_res;
struct resource *pio_res;
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base && physbase && pio_res
&& pio_res->base && lfb_res && lfb_res->base) {
printk(BIOS_SPEW,
"Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
"$VBT IRONLAKE-MOBILE");
}
}
static void native_init(struct device *dev)
{
struct resource *lfb_res;
struct resource *pio_res;
u32 physbase;
struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
struct northbridge_intel_x4x_config *conf = dev->chip_info;
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base) {
printk(BIOS_SPEW,
"Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
physbase, pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");
}
static void gma_func0_init(struct device *dev)
{
u32 reg32;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
} else {
u32 physbase;
struct resource *pio_res;
struct northbridge_intel_pineview_config *conf = dev->chip_info;
/* Find base addresses */
mmio_res = find_resource(dev, 0x10);
gtt_res = find_resource(dev, 0x1c);
pio_res = find_resource(dev, 0x14);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
mmio_res->base);
intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0),
res2mmio(gtt_res, 0, 0),
physbase, pio_res->base);
}
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
"$VBT PINEVIEW ");
}
}