static void model_f4x_init(struct device *cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
}
/* Enable the local CPU APICs */
setup_lapic();
/* Start up my CPU siblings */
intel_sibling_init(cpu);
};
static void model_f3x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);
}
/* Enable the local cpu apics */
setup_lapic();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
};
