struct intel_region *
intel_region_alloc_for_fd(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
int fd, const char *name)
{
struct intel_region *region;
drm_intel_bo *buffer;
int ret;
uint32_t bit_6_swizzle, tiling;
buffer = drm_intel_bo_gem_create_from_prime(screen->bufmgr,
fd, height * pitch);
if (buffer == NULL)
return NULL;
ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer (%s): %s\n",
name, strerror(-ret));
drm_intel_bo_unreference(buffer);
return NULL;
}
region = intel_region_alloc_internal(screen, cpp,
width, height, pitch, tiling, buffer);
if (region == NULL) {
drm_intel_bo_unreference(buffer);
return NULL;
}
return region;
}
struct intel_region *
intel_region_alloc(struct intel_screen *screen,
uint32_t tiling,
GLuint cpp, GLuint width, GLuint height,
bool expect_accelerated_upload)
{
drm_intel_bo *buffer;
unsigned long flags = 0;
unsigned long aligned_pitch;
struct intel_region *region;
if (expect_accelerated_upload)
flags |= BO_ALLOC_FOR_RENDER;
buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region",
width, height, cpp,
&tiling, &aligned_pitch, flags);
if (buffer == NULL)
return NULL;
region = intel_region_alloc_internal(screen, cpp, width, height,
aligned_pitch, tiling, buffer);
if (region == NULL) {
drm_intel_bo_unreference(buffer);
return NULL;
}
return region;
}
struct intel_region *
intel_region_alloc_for_handle(struct intel_context *intel,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
GLuint handle, const char *name)
{
struct intel_region *region;
dri_bo *buffer;
int ret;
buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
region = intel_region_alloc_internal(intel, cpp,
width, height, pitch, buffer);
if (region == NULL)
return region;
ret = dri_bo_get_tiling(region->buffer, ®ion->tiling,
®ion->bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
handle, name, strerror(-ret));
intel_region_release(®ion);
return NULL;
}
return region;
}
struct intel_region *
intel_region_alloc(struct intel_context *intel,
uint32_t tiling,
GLuint cpp, GLuint width, GLuint height, GLuint pitch,
GLboolean expect_accelerated_upload)
{
dri_bo *buffer;
struct intel_region *region;
/* If we're tiled, our allocations are in 8 or 32-row blocks, so
* failure to align our height means that we won't allocate enough pages.
*
* If we're untiled, we still have to align to 2 rows high because the
* data port accesses 2x2 blocks even if the bottom row isn't to be
* rendered, so failure to align means we could walk off the end of the
* GTT and fault.
*/
if (tiling == I915_TILING_X)
height = ALIGN(height, 8);
else if (tiling == I915_TILING_Y)
height = ALIGN(height, 32);
else
height = ALIGN(height, 2);
/* If we're untiled, we have to align to 2 rows high because the
* data port accesses 2x2 blocks even if the bottom row isn't to be
* rendered, so failure to align means we could walk off the end of the
* GTT and fault.
*/
height = ALIGN(height, 2);
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
pitch * cpp * height, 64);
} else {
buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
pitch * cpp * height, 64);
}
region = intel_region_alloc_internal(intel, cpp, width, height,
pitch, buffer);
if (tiling != I915_TILING_NONE) {
assert(((pitch * cpp) & 127) == 0);
drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
drm_intel_bo_get_tiling(buffer, ®ion->tiling, ®ion->bit_6_swizzle);
}
return region;
}
struct intel_region *
intel_region_alloc(struct intel_context *intel,
GLuint cpp, GLuint width, GLuint height, GLuint pitch,
GLboolean expect_accelerated_upload)
{
dri_bo *buffer;
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
pitch * cpp * height, 64);
} else {
buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
pitch * cpp * height, 64);
}
return intel_region_alloc_internal(intel, cpp, width, height, pitch, buffer);
}
