/*
The "current usb host enable timeout" shows the current value of
the variable.
*/
static ssize_t usb_host_enable_timeout_show(struct device *dev,
struct device_attribute *attr, char *buffer)
{
int ret_ipc;
u8 data_read;
int i = 0;
char timeout[MAX_USB_TIMEOUT_LEN];
ret_ipc = intel_scu_ipc_read_mip(&data_read,
1,
USB_ENABLE_UMIP_OFFSET,
0);
if (ret_ipc)
pr_err("Could not read to UMIP USB Host Enable\n");
for (i = 0; i < MAX_NUM_TIMEOUTS; i++) {
if (data_read ==
available_usb_host_enable_timeouts[i].umip_value) {
strcpy(timeout,
available_usb_host_enable_timeouts[i].name);
break;
}
}
if (i == MAX_NUM_TIMEOUTS)
return sprintf(buffer, "%s\n", "Could not read right value");
else
return sprintf(buffer, "%s\n", &timeout);
}
int get_smip_property_by_name(enum platform_prop pp)
{
u8 data[SMIP_MAX_PROP_LEN];
int i, val, ret;
struct smip_platform_prop prop[SMIP_NUM_CONFIG_PROPS];
if (!pdata->smip_prop)
return -EINVAL;
for (i = 0; i < SMIP_NUM_CONFIG_PROPS; i++)
prop[i] = pdata->smip_prop[i];
/* Read the property requested by the caller */
ret = intel_scu_ipc_read_mip(data, prop[pp].len, prop[pp].offset, 1);
if (ret)
return ret;
/* Adjust the bytes according to the length and return the int */
val = data[0];
for (i = 1; i < prop[pp].len; i++)
val = val << 8 | data[i];
/* If the requested property is a bit field, return that bit value */
if (prop[pp].is_bit_field)
val &= prop[pp].mask;
return val;
}
/**
* mfld_fg_restore_config_data - restore config data
* @name : Power Supply name
* @data : config data output pointer
* @len : length of config data
*
*/
int mfld_fg_restore_config_data(const char *name, void *data, int len)
{
int mip_offset, ret;
/* Read the fuel gauge config data from umip */
mip_offset = UMIP_REF_FG_TBL + BATT_FG_TBL_BODY;
ret = intel_scu_ipc_read_mip((u8 *)data, len, mip_offset, 0);
return ret;
}
int ug31xx_read_backup_tag(const char *name, u8 *data)
{
int mip_offset, ret;
pr_debug("%s:\n", __func__);
mip_offset = BATT_UG31_FG_TBL_BODY;
ret = intel_scu_ipc_read_mip(data, 1, mip_offset, 0);
if (ret)
UG31_LOGE("%s: * umip read failed *\n", name);
return ret;
}
ssize_t Factory_UMIP_store(struct device *dev,
struct device_attribute *attr,
const char *buffer, size_t count)
{
int ret = 0;
u8 data_write;
u8 yes;
u8 no;
bool bv;
if (strlen(buffer) != 2) {
pr_err("The length must be 1\n");
ret = -EINVAL;
goto error;
}
ret = strtobool(buffer, &bv);
if (ret) {
pr_err("Not expected value [Y|y|1|N|n|0]\n");
goto error;
}
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL) {
ret = intel_scu_ipc_read_mip(&data_write,
1,
FACTORY_UMIP_OFFSET,
0);
data_write &= ~(1 << FACTORY_BIT_OFFSET);
data_write |= bv;
ret = intel_scu_ipc_write_umip(&data_write,
1,
FACTORY_UMIP_OFFSET);
if (ret) {
pr_err("Could not write to UMIP for Factory\n");
goto error;
}
}
return count;
error:
return ret;
}
static ssize_t factory_umip_show(struct device *dev,
struct device_attribute *attr, char *buffer)
{
int ret;
u8 data_read;
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL) {
ret = intel_scu_ipc_read_mip(&data_read,
1,
FACTORY_UMIP_OFFSET,
0);
if (ret) {
pr_err("Could not read to UMIP for Factory\n");
return -EBUSY;
}
return sprintf(buffer, "%d\n",
(data_read >> FACTORY_BIT_OFFSET) & 0x01);
} else {
static ssize_t mip_cmd_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t size)
{
int ret;
memset(mip_cmd, 0, sizeof(mip_cmd));
ret = sscanf(buf, "%10s", mip_cmd);
if (ret == 0) {
mip_dbg_error = -EINVAL;
goto end;
}
if (!strncmp("read_mip", mip_cmd, MIP_CMD_LEN)) {
memset(mip_data, 0, sizeof(mip_data));
ret = intel_scu_ipc_read_mip(mip_data, mip_len, mip_offset,
mip_issigned);
if (!ret)
valid_data_nr = mip_len;
} else if (!strncmp("write_umip", mip_cmd, MIP_CMD_LEN)) {
if (mip_len == valid_data_nr) {
ret = intel_scu_ipc_write_umip(mip_data, mip_len,
mip_offset);
} else
goto error;
} else
goto error;
if (ret)
goto error;
else
goto end;
error:
mip_dbg_error = -EINVAL;
end:
return size;
}
/**
* init_batt_thresholds - initialize battery thresholds
* @chip: charger driver device context
* Context: can sleep
*/
static void platform_init_battery_threshold(u8 total_temp_range,
struct platform_batt_safety_param *safe_param,
struct platform_batt_profile *batt_profile)
{
int ret;
u8 validate_smip_data[4] = {0};
bool fpo_override_bit = false;
pr_debug("%s:%d:\n", __func__, __LINE__);
safe_param->vbatt_sh_min = BATT_VMIN_THRESHOLD_DEF;
safe_param->vbatt_crit = BATT_CRIT_CUTOFF_VOLT_DEF;
safe_param->temp_high = BATT_TEMP_MAX_DEF;
safe_param->temp_low = BATT_TEMP_MIN_DEF;
/* Read the Signature verification data form SRAM */
ret = intel_scu_ipc_read_mip((u8 *)validate_smip_data,
4,
SMIP_SRAM_OFFSET_ADDR, 1);
if (ret) {
pr_warn("EM:%s:%d:smip read failed\n", __func__, __LINE__);
return;
}
pr_debug("EM:%s: SBCT_REV: 0x%x RSYS_OHMS 0x%x", __func__,
validate_smip_data[0], validate_smip_data[3]);
/* Check for Valid SMIP data */
if ((validate_smip_data[0] == SBCT_REV) && (
validate_smip_data[3] == RSYS_MOHMS)) {
pr_debug("EM:%s: Valid SMIP data\n", __func__);
pr_info("validate_smip_data[1] %x\n", validate_smip_data[1]);
/*
* Check for the override bit FPO[1]. If this is set offset
* would change for right battery parameters while reading
* from SMIP.
*/
if (validate_smip_data[1] & FPO_OVERRIDE_BIT)
fpo_override_bit = true;
/* Read the threshold values from SRAM */
ret = intel_scu_ipc_read_mip((u8 *)safe_param,
sizeof(struct platform_batt_safety_param),
SMIP_SRAM_OFFSET_ADDR, 1);
if (ret) {
pr_warn("EM:%s:smip read failed\n", __func__);
return;
}
pr_info("%s:sh_min - %x\n", __func__,
safe_param->vbatt_sh_min);
/* Read the battery properties from SRAM */
/* BATTID_STR_LEN -> length of the battid
* +1 -> number of temp_mon_ranges
* SMIP_SRAM_BATT_PROP_OFFSET+4 -> ignore b1idmin and b1idmax
*/
}
/* Get the battery profile */
platform_get_sfi_batt_table(batt_profile, fpo_override_bit);
if (batt_profile->temp_mon_ranges == 0) {
/* BELOW CODE WILL BE USED IN INVALID BATTERY
DO WE NEED TO USE CHARGE PROFILE FOR INVALID BATTERY? */
batt_profile->temp_mon_ranges = total_temp_range;
/* store the default parameters */
/* Define the temperature ranges */
if (batt_profile->temp_mon_ranges == 4) {
batt_profile->temp_mon_range[0].temp_up_lim = 60;
batt_profile->temp_mon_range[0].temp_low_lim = 45;
batt_profile->temp_mon_range[0].full_chrg_vol = 4200;
batt_profile->temp_mon_range[0].full_chrg_cur = 1216;
batt_profile->temp_mon_range[0].maint_chrg_vol_ll = 4100;
batt_profile->temp_mon_range[0].maint_chrg_vol_ul = 4200;
batt_profile->temp_mon_range[0].maint_chrg_cur = 1216;
batt_profile->temp_mon_range[1].temp_up_lim = 45;
batt_profile->temp_mon_range[1].temp_low_lim = 0;
batt_profile->temp_mon_range[1].full_chrg_vol = 4320;
batt_profile->temp_mon_range[1].full_chrg_cur = 1216;
batt_profile->temp_mon_range[1].maint_chrg_vol_ll = 4220;
batt_profile->temp_mon_range[1].maint_chrg_vol_ul = 4320;
batt_profile->temp_mon_range[1].maint_chrg_cur = 1216;
batt_profile->temp_mon_range[2].temp_up_lim = 10;
batt_profile->temp_mon_range[2].full_chrg_vol = 4320;
batt_profile->temp_mon_range[2].full_chrg_cur = 1216;
batt_profile->temp_mon_range[2].maint_chrg_vol_ll = 4220;
batt_profile->temp_mon_range[2].maint_chrg_vol_ul = 4320;
batt_profile->temp_mon_range[2].maint_chrg_cur = 1216;
batt_profile->temp_mon_range[3].temp_up_lim = 0;
batt_profile->temp_mon_range[3].temp_low_lim = -10;
batt_profile->temp_mon_range[3].full_chrg_vol = 0;
batt_profile->temp_mon_range[3].full_chrg_cur = 0;
batt_profile->temp_mon_range[3].maint_chrg_vol_ll = 0;
batt_profile->temp_mon_range[3].maint_chrg_vol_ul = 0;
batt_profile->temp_mon_range[3].maint_chrg_cur = 0;
}
}
platform_get_batt_temp_thresholds(batt_profile,
&safe_param->temp_high,
&safe_param->temp_low);
}
/**
* scu_ipc_ioctl - control ioctls for the SCU
* @fp: file handle of the SCU device
* @cmd: ioctl coce
* @arg: pointer to user passed structure
*
* Support the I/O and firmware flashing interfaces of the SCU
*/
static long scu_ipc_ioctl(struct file *fp, unsigned int cmd,
unsigned long arg)
{
int ret = -EINVAL;
struct scu_ipc_data data;
void __user *argp = (void __user *)arg;
int platform;
/* Only IOCTL cmd allowed to pass through without capability check */
/* is getting fw version info, all others need to check to prevent */
/* arbitrary access to all sort of bit of the hardware exposed here*/
if (cmd != INTEL_SCU_IPC_FW_REVISION_GET && !capable(CAP_SYS_RAWIO))
return -EPERM;
platform = intel_mid_identify_cpu();
switch (cmd) {
case INTEL_SCU_IPC_READ_FBMODE_FROM_OSNIB:
{
u8 fb_mode;
ret = intel_scu_ipc_read_osnib_fb_mode(&fb_mode);
if (ret < 0) {
pr_err("read fb_mode from ipc failed!!\n");
return ret;
}
ret = copy_to_user(argp, &fb_mode, 1);
break;
}
case INTEL_SCU_IPC_WRITE_FBMODE_TO_OSNIB:
{
u8 fb_mode;
ret = copy_from_user(&fb_mode, (u8 *)arg, 1);
if (ret < 0) {
pr_err("copy fb_mode from user failed!!\n");
return ret;
}
ret = intel_scu_ipc_write_osnib_fb_mode(fb_mode);
break;
}
case INTEL_SCU_IPC_READ_BOS_FROM_OSNIB:
{
u8 resync_reason;
ret = intel_scu_ipc_read_osnib_bos(&resync_reason);
if (ret < 0)
return ret;
ret = copy_to_user(argp, &resync_reason, 1);
break;
}
case INTEL_SCU_IPC_WRITE_BOS_TO_OSNIB:
{
u8 data;
ret = copy_from_user(&data, (u8 *)arg, 1);
if (ret < 0) {
pr_err("copy from user failed!!\n");
return ret;
}
ret = intel_scu_ipc_write_osnib_bos(data);
break;
}
case INTEL_SCU_IPC_READ_RR_FROM_OSNIB:
{
u8 reboot_reason;
ret = intel_scu_ipc_read_osnib_rr(&reboot_reason);
if (ret < 0)
return ret;
ret = copy_to_user(argp, &reboot_reason, 1);
break;
}
case INTEL_SCU_IPC_WRITE_RR_TO_OSNIB:
{
u8 data;
ret = copy_from_user(&data, (u8 *)arg, 1);
if (ret < 0) {
pr_err("copy from user failed!!\n");
return ret;
}
ret = intel_scu_ipc_write_osnib_rr(data);
break;
}
case INTEL_SCU_IPC_WRITE_ALARM_FLAG_TO_OSNIB:
{
u8 flag, data;
ret = copy_from_user(&flag, (u8 *)arg, 1);
if (ret < 0) {
pr_err("copy from user failed!!\n");
return ret;
}
ret = intel_scu_ipc_read_osnib(&data, 1, OSNIB_ALARM_OFFSET);
if (ret < 0)
return ret;
if (flag)
data = data | 0x1; /* set alarm flag */
else
data = data & 0xFE; /* clear alarm flag */
ret = intel_scu_ipc_write_osnib(&data, 1, OSNIB_ALARM_OFFSET);
break;
}
case INTEL_SCU_IPC_READ_VBATTCRIT:
{
u32 value;
pr_debug("cmd = INTEL_SCU_IPC_READ_VBATTCRIT");
ret = intel_scu_ipc_read_mip((u8 *)&value, 4, 0x318, 1);
if (ret < 0)
return ret;
pr_debug("VBATTCRIT VALUE = %x\n", value);
ret = copy_to_user(argp, &value, 4);
break;
}
case INTEL_SCU_IPC_FW_REVISION_GET:
{
struct scu_ipc_version version;
if (copy_from_user(&version, argp, sizeof(u32)))
return -EFAULT;
if (version.count > 16)
return -EINVAL;
ret = intel_scu_ipc_command(IPCMSG_FW_REVISION, 0,
NULL, 0, (u32 *)version.data, 4);
if (ret < 0)
return ret;
if (copy_to_user(argp + sizeof(u32),
version.data, version.count))
ret = -EFAULT;
break;
}
case INTEL_SCU_IPC_OSC_CLK_CNTL:
{
struct osc_clk_t osc_clk;
if (copy_from_user(&osc_clk, argp, sizeof(struct osc_clk_t)))
return -EFAULT;
ret = intel_scu_ipc_osc_clk(osc_clk.id, osc_clk.khz);
if (ret)
pr_err("%s: failed to set osc clk\n", __func__);
break;
}
case INTEL_SCU_IPC_READ_BYTE_IN_OSNIB:
{
struct osnib_data read_data;
ret = copy_from_user(&read_data, (u8 *)arg,
sizeof(struct scu_ipc_data));
if (ret < 0) {
pr_err("copy from user failed!!\n");
return ret;
}
if ((read_data.offset-OSNIB_OFFSET) >= 32)
return -EINVAL;
ret = intel_scu_ipc_read_osnib_byte(read_data.offset,
&read_data.data);
if (ret < 0)
return ret;
ret = copy_to_user(argp, &read_data,
sizeof(struct scu_ipc_data));
break;
}
case INTEL_SCU_IPC_WRITE_BYTE_IN_OSNIB:
{
struct osnib_data write_data;
ret = copy_from_user(&write_data, (u8 *)arg,
sizeof(struct scu_ipc_data));
if (ret < 0) {
pr_err("copy from user failed!!\n");
return ret;
}
if ((write_data.offset-OSNIB_OFFSET) >= 32)
return -EINVAL;
ret = intel_scu_ipc_write_osnib_byte(write_data.offset,
write_data.data);
if (ret < 0)
return ret;
break;
}
default:
if (copy_from_user(&data, argp, sizeof(struct scu_ipc_data)))
return -EFAULT;
ret = scu_reg_access(cmd, &data);
if (ret < 0)
return ret;
if (copy_to_user(argp, &data, sizeof(struct scu_ipc_data)))
return -EFAULT;
return 0;
}
return ret;
}
