static void guc_init_send_regs(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); enum forcewake_domains fw_domains = 0; unsigned int i; guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); guc->send_regs.count = SOFT_SCRATCH_COUNT - 1; for (i = 0; i < guc->send_regs.count; i++) { fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, guc_send_reg(guc, i), FW_REG_READ | FW_REG_WRITE); } guc->send_regs.fw_domains = fw_domains; }
for_each_engine(engine, i915, id) { i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; enum forcewake_domains fw_domains; u32 val; if (!engine->default_state) continue; fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio, FW_REG_READ); if (!fw_domains) continue; for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { if (!domain->wake_count) continue; pr_err("fw_domain %s still active, aborting test!\n", intel_uncore_forcewake_domain_to_str(domain->id)); err = -EINVAL; goto out_rpm; } intel_uncore_forcewake_get(uncore, fw_domains); val = readl(reg); intel_uncore_forcewake_put(uncore, fw_domains); /* Flush the forcewake release (delayed onto a timer) */ for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { smp_store_mb(domain->active, false); if (hrtimer_cancel(&domain->timer)) intel_uncore_fw_release_timer(&domain->timer); preempt_disable(); err = wait_ack_clear(domain, FORCEWAKE_KERNEL); preempt_enable(); if (err) { pr_err("Failed to clear fw_domain %s\n", intel_uncore_forcewake_domain_to_str(domain->id)); goto out_rpm; } }