static void
setgtt(int start, int end, unsigned long base, int inc)
{
int i;
for(i = start; i < end; i++){
u32 word = base + i*inc;
io_i915_write32(word|1,(i*4)|1);
}
}
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port)
{
int wait = 0;
uint32_t val;
if (io_i915_read32(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
val = io_i915_read32(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
io_i915_write32(DDI_BUF_CTL(port), val);
wait = 1;
}
val = io_i915_read32(DP_TP_CTL(port));
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
io_i915_write32(DP_TP_CTL(port), val);
//POSTING_READ(DP_TP_CTL(port));
if (wait)
intel_wait_ddi_buf_idle(port);
}
val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
io_i915_write32(DP_TP_CTL(port), val);
//POSTING_READ(DP_TP_CTL(port));
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
io_i915_write32(DDI_BUF_CTL(port), intel_dp->DP);
//POSTING_READ(DDI_BUF_CTL(port));
udelay(600);
}
/* On Haswell, DDI port buffers must be programmed with correct values
* in advance. The buffer values are different for FDI and DP modes,
* but the HDMI/DVI fields are shared among those. So we program the DDI
* in either FDI or DP modes only, as HDMI connections will work with both
* of those.
*/
void intel_prepare_ddi_buffers(int port, int use_fdi_mode)
{
u32 reg;
int i;
u32 *ddi_translations = ((use_fdi_mode) ?
hsw_ddi_translations_fdi :
hsw_ddi_translations_dp);
printk(BIOS_SPEW, "Initializing DDI buffers for port %d in %s mode\n",
port,
use_fdi_mode ? "FDI" : "DP");
for (i=0,reg=DDI_BUF_TRANS(port);i < ARRAY_SIZE(hsw_ddi_translations_fdi);i++) {
io_i915_write32(ddi_translations[i], reg);
reg += 4;
}
}
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
{
io_i915_write32(0x80000000,0x45400);
io_i915_write32(0x00000000,_CURACNTR);
io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
io_i915_write32(0x00000000,_DSPBCNTR);
io_i915_write32(0x80000000,CPU_VGACNTRL);
io_i915_write32(0x00000000,_DSPASIZE+0xc);
io_i915_write32(0x00000000,_DSPBSURF);
io_i915_write32(0x00000000,0x4f050);
io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
DP_SYNC_VS_HIGH |0x00000091,DP_A);
io_i915_write32(0x00200090,_FDI_RXA_MISC);
io_i915_write32(0x0a000000,_FDI_RXA_MISC);
/* not yet documented anywhere that we can find. */
io_i915_write32(0x00000070,0x46408);
io_i915_write32(0x04000000,0x42090);
io_i915_write32(0x40000000,0x4f050);
io_i915_write32(0x00000000,0x9840);
io_i915_write32(0xa4000000,0x42090);
io_i915_write32(0x00004000,0x42080);
io_i915_write32(0x00ffffff,0x64f80);
io_i915_write32(0x0007000e,0x64f84);
io_i915_write32(0x00d75fff,0x64f88);
io_i915_write32(0x000f000a,0x64f8c);
io_i915_write32(0x00c30fff,0x64f90);
io_i915_write32(0x00060006,0x64f94);
io_i915_write32(0x00aaafff,0x64f98);
io_i915_write32(0x001e0000,0x64f9c);
io_i915_write32(0x00ffffff,0x64fa0);
io_i915_write32(0x000f000a,0x64fa4);
io_i915_write32(0x00d75fff,0x64fa8);
io_i915_write32(0x00160004,0x64fac);
io_i915_write32(0x00c30fff,0x64fb0);
io_i915_write32(0x001e0000,0x64fb4);
io_i915_write32(0x00ffffff,0x64fb8);
io_i915_write32(0x00060006,0x64fbc);
io_i915_write32(0x00d75fff,0x64fc0);
io_i915_write32(0x001e0000,0x64fc4);
io_i915_write32(0x00ffffff,0x64e00);
io_i915_write32(0x0006000e,0x64e04);
io_i915_write32(0x00d75fff,0x64e08);
io_i915_write32(0x0005000a,0x64e0c);
io_i915_write32(0x00c30fff,0x64e10);
io_i915_write32(0x00040006,0x64e14);
io_i915_write32(0x80aaafff,0x64e18);
io_i915_write32(0x000b0000,0x64e1c);
io_i915_write32(0x00ffffff,0x64e20);
io_i915_write32(0x0005000a,0x64e24);
io_i915_write32(0x00d75fff,0x64e28);
io_i915_write32(0x000c0004,0x64e2c);
io_i915_write32(0x80c30fff,0x64e30);
io_i915_write32(0x000b0000,0x64e34);
io_i915_write32(0x00ffffff,0x64e38);
io_i915_write32(0x00040006,0x64e3c);
io_i915_write32(0x80d75fff,0x64e40);
io_i915_write32(0x000b0000,0x64e44);
/* end not yet documented. */
io_i915_write32(0x10000000,SDEISR+0x30);
}
int i915lightup(unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx)
{
int must_cycle_power = 0;
/* frame buffer pointer */
u32 *l;
int i;
unsigned long before_gtt, after_gtt;
mmio = (void *)pmmio;
addrport = piobase;
dataport = addrport + 4;
physbase = pphysbase;
graphics = pgfx;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p"
"addrport %04x physbase %08x\n",
(void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll();
/* turn it on. The VBIOS does it this way, so we hope that's ok. */
verbose = 0;
io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
/* the AUX channel needs a small amount of time to spin up.
* Rather than udelay, do some useful work:
* Zero out the frame buffer memory,
* and set the global translation table (GTT)
*/
printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
FRAME_BUFFER_BYTES/sizeof(u32));
for(l = (u32 *)graphics, i = 0;
i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
l[i] = 0x1122ff;
}
printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
FRAME_BUFFER_PAGES, (void *)physbase);
before_gtt = globalmicroseconds();
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
after_gtt = globalmicroseconds();
/* The reset is basically harmless, and can be
* repeated by the VBIOS in any event.
*/
graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
/* failures after this point can return without
* powering off the panel.
*/
if (1)
goto fail;
/* failures after this point MUST power off the panel
* and wait 600 ms.
*/
i915_init_done = 1;
oprom_is_loaded = 1;
return 1;
fail:
printk(BIOS_SPEW, "Graphics could not be started;");
if (must_cycle_power){
printk(BIOS_SPEW, "Turn off power and wait ...");
io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
udelay(600000);
}
printk(BIOS_SPEW, "Returning.\n");
return 0;
}