static void iomd_enable_dma(unsigned int chan, dma_t *dma) { struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); unsigned long dma_base = idma->base; unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; if (idma->dma.invalid) { idma->dma.invalid = 0; /* */ if (!idma->dma.sg) { idma->dma.sg = &idma->dma.buf; idma->dma.sgcount = 1; idma->dma.buf.length = idma->dma.count; idma->dma.buf.dma_address = dma_map_single(NULL, idma->dma.addr, idma->dma.count, idma->dma.dma_mode == DMA_MODE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); } iomd_writeb(DMA_CR_C, dma_base + CR); idma->state = DMA_ST_AB; } if (idma->dma.dma_mode == DMA_MODE_READ) ctrl |= DMA_CR_D; iomd_writeb(ctrl, dma_base + CR); enable_irq(idma->irq); }
static void iomd_enable_dma(dmach_t channel, dma_t *dma) { unsigned long dma_base = dma->dma_base; unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; if (dma->invalid) { dma->invalid = 0; /* * Cope with ISA-style drivers which expect cache * coherence. */ if (!dma->using_sg) { dma->buf.dma_address = pci_map_single(NULL, dma->buf.__address, dma->buf.length, dma->dma_mode == DMA_MODE_READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); } iomd_writeb(DMA_CR_C, dma_base + CR); dma->state = DMA_ST_AB; } if (dma->dma_mode == DMA_MODE_READ) ctrl |= DMA_CR_D; iomd_writeb(ctrl, dma_base + CR); enable_irq(dma->dma_irq); }
int __init psaux_init(void) { /* Reset the mouse state machine. */ iomd_writeb(0, IOMD_MSECTL); iomd_writeb(8, IOMD_MSECTL); queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL); if (queue == NULL) return -ENOMEM; if (misc_register(&psaux_mouse)) { kfree(queue); return -ENODEV; } memset(queue, 0, sizeof(*queue)); queue->head = queue->tail = 0; init_waitqueue_head(&queue->proc_list); aux_write_ack(AUX_SET_SAMPLE); aux_write_ack(100); /* 100 samples/sec */ aux_write_ack(AUX_SET_RES); aux_write_ack(3); /* 8 counts per mm */ aux_write_ack(AUX_SET_SCALE21); /* 2:1 scaling */ return 0; }
static void iomd_ack_irq_a(struct irq_data *d) { unsigned int val, mask; mask = 1 << d->irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_writeb(mask, IOMD_IRQCLRA); }
static void cl7500_ack_irq_a(unsigned int irq) { unsigned int val, mask; mask = 1 << irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_writeb(mask, IOMD_IRQCLRA); }
void __init rpc_init_irq(void) { unsigned int irq, clr, set = 0; iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKB); iomd_writeb(0, IOMD_FIQMASK); iomd_writeb(0, IOMD_DMAMASK); set_fiq_handler(&rpc_default_fiq_start, &rpc_default_fiq_end - &rpc_default_fiq_start); for (irq = 0; irq < NR_IRQS; irq++) { clr = IRQ_NOREQUEST; if (irq <= 6 || (irq >= 9 && irq <= 15)) clr |= IRQ_NOPROBE; if (irq == 21 || (irq >= 16 && irq <= 19) || irq == IRQ_KEYBOARDTX) set |= IRQ_NOAUTOEN; switch (irq) { case 0 ... 7: irq_set_chip_and_handler(irq, &iomd_a_chip, handle_level_irq); irq_modify_status(irq, clr, set); break; case 8 ... 15: irq_set_chip_and_handler(irq, &iomd_b_chip, handle_level_irq); irq_modify_status(irq, clr, set); break; case 16 ... 21: irq_set_chip_and_handler(irq, &iomd_dma_chip, handle_level_irq); irq_modify_status(irq, clr, set); break; case 64 ... 71: irq_set_chip(irq, &iomd_fiq_chip); irq_modify_status(irq, clr, set); break; } } init_FIQ(FIQ_START); }
void __init rpc_init_irq(void) { unsigned int irq, flags; iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKB); iomd_writeb(0, IOMD_FIQMASK); iomd_writeb(0, IOMD_DMAMASK); for (irq = 0; irq < NR_IRQS; irq++) { flags = IRQF_VALID; if (irq <= 6 || (irq >= 9 && irq <= 15)) flags |= IRQF_PROBE; if (irq == 21 || (irq >= 16 && irq <= 19) || irq == IRQ_KEYBOARDTX) flags |= IRQF_NOAUTOEN; switch (irq) { case 0 ... 7: irq_set_chip_and_handler(irq, &iomd_a_chip, handle_level_irq); set_irq_flags(irq, flags); break; case 8 ... 15: irq_set_chip_and_handler(irq, &iomd_b_chip, handle_level_irq); set_irq_flags(irq, flags); break; case 16 ... 21: irq_set_chip_and_handler(irq, &iomd_dma_chip, handle_level_irq); set_irq_flags(irq, flags); break; case 64 ... 71: irq_set_chip(irq, &iomd_fiq_chip); set_irq_flags(irq, IRQF_VALID); break; } } init_FIQ(); }
static void iomd_mask_irq_fiq(unsigned int irq) { unsigned int val, mask; mask = 1 << (irq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val & ~mask, IOMD_FIQMASK); }
/* * Send a byte to the mouse & handle returned ack */ static void aux_write_ack(int val) { while (!(iomd_readb(IOMD_MSECTL) & 0x80)); iomd_writeb(val, IOMD_MSEDAT); /* we expect an ACK in response. */ mouse_reply_expected++; }
static void iomd_mask_irq_dma(struct irq_data *d) { unsigned int val, mask; mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_DMAMASK); iomd_writeb(val & ~mask, IOMD_DMAMASK); }
static void iomd_unmask_irq_a(unsigned int irq) { unsigned int val, mask; mask = 1 << irq; val = iomd_readb(IOMD_IRQMASKA); iomd_writeb(val | mask, IOMD_IRQMASKA); }
static void cl7500_mask_irq_b(unsigned int irq) { unsigned int val, mask; mask = 1 << (irq & 7); val = iomd_readb(IOMD_IRQMASKB); iomd_writeb(val & ~mask, IOMD_IRQMASKB); }
static void cl7500_unmask_irq_c(unsigned int irq) { unsigned int val, mask; mask = 1 << (irq & 7); val = iomd_readb(IOMD_IRQMASKC); iomd_writeb(val | mask, IOMD_IRQMASKC); }
static void iomd_unmask_irq_fiq(struct irq_data *d) { unsigned int val, mask; mask = 1 << (d->irq & 7); val = iomd_readb(IOMD_FIQMASK); iomd_writeb(val | mask, IOMD_FIQMASK); }
static void iomd_unmask_irq_dma(unsigned int irq) { unsigned int val, mask; mask = 1 << (irq & 7); val = iomd_readb(IOMD_DMAMASK); iomd_writeb(val | mask, IOMD_DMAMASK); }
static void rpc_restart(char mode, const char *cmd) { iomd_writeb(0, IOMD_ROMCR0); /* * Jump into the ROM */ soft_restart(0); }
static int rpckbd_write(struct serio *port, unsigned char val) { while (!(iomd_readb(IOMD_KCTRL) & (1 << 7))) cpu_relax(); iomd_writeb(val, IOMD_KARTTX); return 0; }
static void iomd_disable_dma(dmach_t channel, dma_t *dma) { unsigned long dma_base = dma->dma_base; unsigned int ctrl; disable_irq(dma->dma_irq); ctrl = iomd_readb(dma_base + CR); iomd_writeb(ctrl & ~DMA_CR_E, dma_base + CR); }
static void iomd_disable_dma(dmach_t channel, dma_t *dma) { unsigned long dma_base = dma->dma_base; unsigned long flags; local_irq_save(flags); if (dma->state != ~DMA_ST_AB) disable_irq(dma->dma_irq); iomd_writeb(0, dma_base + CR); local_irq_restore(flags); }
static int rpckbd_open(struct serio *port) { /* Reset the keyboard state machine. */ iomd_writeb(0, IOMD_KCTRL); iomd_writeb(8, IOMD_KCTRL); iomd_readb(IOMD_KARTRX); if (request_irq(IRQ_KEYBOARDRX, rpckbd_rx, 0, "rpckbd", port) != 0) { printk(KERN_ERR "rpckbd.c: Could not allocate keyboard receive IRQ\n"); return -EBUSY; } if (request_irq(IRQ_KEYBOARDTX, rpckbd_tx, 0, "rpckbd", port) != 0) { printk(KERN_ERR "rpckbd.c: Could not allocate keyboard transmit IRQ\n"); free_irq(IRQ_KEYBOARDRX, NULL); return -EBUSY; } return 0; }
static void iomd_disable_dma(unsigned int chan, dma_t *dma) { struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); unsigned long dma_base = idma->base; unsigned long flags; local_irq_save(flags); if (idma->state != ~DMA_ST_AB) disable_irq(idma->irq); iomd_writeb(0, dma_base + CR); local_irq_restore(flags); }
static int rpckbd_open(struct serio *port) { struct rpckbd_data *rpckbd = port->port_data; iomd_writeb(0, IOMD_KCTRL); iomd_writeb(8, IOMD_KCTRL); iomd_readb(IOMD_KARTRX); if (request_irq(rpckbd->rx_irq, rpckbd_rx, 0, "rpckbd", port) != 0) { printk(KERN_ERR "rpckbd.c: Could not allocate keyboard receive IRQ\n"); return -EBUSY; } if (request_irq(rpckbd->tx_irq, rpckbd_tx, 0, "rpckbd", port) != 0) { printk(KERN_ERR "rpckbd.c: Could not allocate keyboard transmit IRQ\n"); free_irq(rpckbd->rx_irq, port); return -EBUSY; } return 0; }
static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle) { int tcr, speed; if (cycle < 188) speed = 3; else if (cycle <= 250) speed = 2; else if (cycle < 438) speed = 1; else speed = 0; tcr = iomd_readb(IOMD_DMATCR); speed &= 3; switch (channel) { case DMA_0: tcr = (tcr & ~0x03) | speed; break; case DMA_1: tcr = (tcr & ~0x0c) | (speed << 2); break; case DMA_2: tcr = (tcr & ~0x30) | (speed << 4); break; case DMA_3: tcr = (tcr & ~0xc0) | (speed << 6); break; default: break; } iomd_writeb(tcr, IOMD_DMATCR); return speed; }
void __init arch_dma_init(dma_t *dma) { iomd_writeb(0, IOMD_IO0CR); iomd_writeb(0, IOMD_IO1CR); iomd_writeb(0, IOMD_IO2CR); iomd_writeb(0, IOMD_IO3CR); iomd_writeb(0xa0, IOMD_DMATCR); dma[DMA_0].dma_base = IOMD_IO0CURA; dma[DMA_0].dma_irq = IRQ_DMA0; dma[DMA_0].d_ops = &iomd_dma_ops; dma[DMA_1].dma_base = IOMD_IO1CURA; dma[DMA_1].dma_irq = IRQ_DMA1; dma[DMA_1].d_ops = &iomd_dma_ops; dma[DMA_2].dma_base = IOMD_IO2CURA; dma[DMA_2].dma_irq = IRQ_DMA2; dma[DMA_2].d_ops = &iomd_dma_ops; dma[DMA_3].dma_base = IOMD_IO3CURA; dma[DMA_3].dma_irq = IRQ_DMA3; dma[DMA_3].d_ops = &iomd_dma_ops; dma[DMA_S0].dma_base = IOMD_SD0CURA; dma[DMA_S0].dma_irq = IRQ_DMAS0; dma[DMA_S0].d_ops = &iomd_dma_ops; dma[DMA_S1].dma_base = IOMD_SD1CURA; dma[DMA_S1].dma_irq = IRQ_DMAS1; dma[DMA_S1].d_ops = &iomd_dma_ops; dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA; dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops; dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops; /* * Setup DMA channels 2,3 to be for podules * and channels 0,1 for internal devices */ iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); }
static void __init clps7500_init_irq(void) { unsigned int irq, flags; iomd_writeb(0, IOMD_IRQMASKA); iomd_writeb(0, IOMD_IRQMASKB); iomd_writeb(0, IOMD_FIQMASK); iomd_writeb(0, IOMD_DMAMASK); for (irq = 0; irq < NR_IRQS; irq++) { flags = IRQF_VALID; if (irq <= 6 || (irq >= 9 && irq <= 15) || (irq >= 48 && irq <= 55)) flags |= IRQF_PROBE; switch (irq) { case 0 ... 7: set_irq_chip(irq, &clps7500_a_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 8 ... 15: set_irq_chip(irq, &clps7500_b_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 16 ... 22: set_irq_chip(irq, &clps7500_dma_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 24 ... 31: set_irq_chip(irq, &clps7500_c_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 40 ... 47: set_irq_chip(irq, &clps7500_d_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 48 ... 55: set_irq_chip(irq, &clps7500_no_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; case 64 ... 72: set_irq_chip(irq, &clps7500_fiq_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, flags); break; } } setup_irq(IRQ_ISA, &irq_isa); }
/* * Send a byte to the mouse. */ static void aux_write_dev(int val) { while (!(iomd_readb(IOMD_MSECTL) & 0x80)); iomd_writeb(val, IOMD_MSEDAT); }