/**
* Update the IOMUX settings where SCM-A11 Ref. varies from the other products.
*/
void __init scma11ref_iomux_mux_fixup(void)
{
/*
* SCM-A11 Package Pin Name: IPU_D3_SPL
* SCM-A11 Reference P1D Wingboard Signal: GPIO_MAIN_BKL (Backlight)
* Selected Primary Function: GP_AP_A30 (Output)
*
* Primary function out of reset: IPU_D3_SPL
* Out of Reset State: Low
* Mux0 Function: GP_AP_A30
*/
iomux_config_mux(AP_IPU_D3_PS, OUTPUTCONFIG_DEFAULT, INPUTCONFIG_NONE);
/*
* SCM-A11 Package Pin Name: GP_AP_C14
* SCM-A11 Reference P1A Wingboard Signal: GPIO_CLI_BKL (Backlight)
* SCM-A11 Reference P1D Wingboard Signal: GPIO_CLI_BKL (Backlight)
* Selected Primary Function: GP_AP_C14 (Output)
*
* Primary function out of reset: GP_AP_C14
* Out of Reset State: Input
* Mux0 Function: GP_AP_C14
*/
iomux_config_mux(AP_GPIO_AP_C14, OUTPUTCONFIG_DEFAULT, INPUTCONFIG_NONE);
}
/*!
* mxc91231_tcs_mod_exit() - de-initialize
* This is called from mx2-ocd.c
*/
void mxc91231_tcd_mod_exit (void)
{
struct otg_instance *otg = tcd_instance->otg;
TRACE_MSG0(TCD, "MX2_MOD_TCD_EXIT");
mxc_iomux_gpio_mc13783_reset ();
#if 0
#if defined(CONFIG_ARCH_MXC91231)
iomux_config_mux(SP_USB_TXOE_B, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
iomux_config_mux(SP_USB_DAT_VP, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
iomux_config_mux(SP_USB_SE0_VM, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
iomux_config_mux(SP_USB_RXD, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
#endif
#if defined(CONFIG_MACH_I30030EVB) || defined(CONFIG_ARCH_I30030EVB)
iomux_config_mux(PIN_USB_XRXD, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_TXENB, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
#endif /* CONFIG_ARCH_I30030EVB */
#endif
mxc_mc13783_mod_exit();
mxc91231_tcd_instance = otg_set_tcd_ops(NULL);
}
/*!
* Setup GPIO for an I2C device to be active
*
* @param i2c_num an I2C device
*/
void gpio_i2c_active(int i2c_num)
{
switch (i2c_num) {
case 0:
iomux_config_mux(AP_I2CLK, OUTPUTCONFIG_FUNC1,
INPUTCONFIG_FUNC1);
iomux_config_mux(AP_I2DAT, OUTPUTCONFIG_FUNC1,
INPUTCONFIG_FUNC1);
default:
break;
}
}
/**
* This function is called by mxc_board_init() at boot time.
*/
void __init argonlvphone_gpio_init(void)
{
unsigned i;
#if defined(CONFIG_MACH_BUTEREF)
buteref_gpio_signal_fixup();
#elif defined(CONFIG_MOT_FEAT_GPIO_API_GPU)
gpu_gpio_signal_fixup();
#endif
/* configure ArgonLV IOMUX pad registers to initial state */
argonlv_iomux_pad_init();
#if !defined(CONFIG_MACH_BUTEREF)
/*
* Care must be taken when transferring pin GPIO24 from Func mux set setting
* to the the GPIO mux setting. GPIO24 is connected to the WDOG_AP signal;
* if the logical value on the pin falls, the phone will shut down.
*/
iomux_config_mux(PIN_GPIO29, OUTPUTCONFIG_ALT5, INPUTCONFIG_NONE);
gpio_signal_config(GPIO_SIGNAL_WDOG_AP, GPIO_GDIR_OUTPUT, GPIO_INT_NONE);
gpio_signal_set_data(GPIO_SIGNAL_WDOG_AP, GPIO_DATA_HIGH);
iomux_config_mux(PIN_GPIO24, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
#endif
/* configure GPIO registers to desired initial state */
for(i = 0; i < MAX_GPIO_SIGNAL; i++) {
if(initial_gpio_settings[i].port != GPIO_INVALID_PORT) {
gpio_tracemsg("GPIO port: 0x%08x signal: 0x%08x output: 0x%08x "
"data: 0x%08x",
initial_gpio_settings[i].port,
initial_gpio_settings[i].sig_no,
initial_gpio_settings[i].out,
initial_gpio_settings[i].data);
/* set data */
if(initial_gpio_settings[i].data != GPIO_DATA_INVALID) {
gpio_set_data(initial_gpio_settings[i].port,
initial_gpio_settings[i].sig_no,
initial_gpio_settings[i].data);
}
/* set direction */
gpio_config(initial_gpio_settings[i].port,
initial_gpio_settings[i].sig_no,
initial_gpio_settings[i].out,
GPIO_INT_NONE); /* setup interrupts later */
}
}
/* configure IOMUX settings to their prescribed initial state */
argonlv_iomux_mux_init();
}
/*!
* Setup GPIO for an I2C device to be inactive
*
* @param i2c_num an I2C device
*/
void gpio_i2c_inactive(int i2c_num)
{
switch (i2c_num) {
case 0:
iomux_config_mux(PIN_I2C_CLK, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
iomux_config_mux(PIN_I2C_DAT, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
break;
default:
break;
}
}
/*!
* Setup GPIO for an I2C device to be inactive
*
* @param i2c_num an I2C device
*/
void gpio_i2c_inactive(int i2c_num)
{
switch (i2c_num) {
case 0:
iomux_config_mux(AP_I2CLK, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
iomux_config_mux(AP_I2DAT, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
break;
default:
break;
}
}
/*!
* This function configures the IOMux block for MC13783 standard operations.
*
*/
void gpio_mc13783_active(void)
{
iomux_config_mux(AP_ED_INT5, OUTPUTCONFIG_FUNC1, INPUTCONFIG_FUNC1);
// edio_config(ED_INT5, 0, EDIO_INT_RISE_EDGE);
#ifdef MXC91231_EVB_PASS1
#ifdef MXC91231_EVB_PASS1_SSI1
iomux_config_mux(AP_GPIO_AP_C8, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
#endif
#ifdef MXC91231_EVB_PASS1_SSI2
iomux_config_mux(AP_GPIO_AP_C16, OUTPUTCONFIG_FUNC1, INPUTCONFIG_FUNC1);
#endif
#endif
}
/*!
* REVISIT: document me
*/
static int __init mxc_init_extuart(void)
{
/*!
* 16C652 UART-A and UART-B interrupt pins are connected to
* e_GPIO24 and e_GPIO25. They are routed to ED_INT6 and ED_INT7
* by configuring the IOMUX and EDIO.
*/
/* UART-A */
iomux_config_mux(PIN_GPIO24, OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1);
set_irq_type(serial_platform_data[0].irq, IRQF_TRIGGER_HIGH);
/* UART-B */
iomux_config_mux(PIN_GPIO25, OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1);
set_irq_type(serial_platform_data[1].irq, IRQF_TRIGGER_HIGH);
return platform_device_register(&serial_device);
}
/*!
* Setup 1-Wire to be active
*/
void gpio_owire_inactive(void)
{
/*
* Configure the IOMUX control register for 1-wire signals.
*/
iomux_config_mux(AP_OWDAT, OUTPUTCONFIG_DEFAULT, INPUTCONFIG_DEFAULT);
}
/*!
* Setup 1-Wire to be active
*/
void gpio_owire_inactive(void)
{
/*
* Configure the IOMUX control register for 1-wire signals.
*/
iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
}
/*!
* Setup 1-Wire to be active
*/
void gpio_owire_active(void)
{
/*
* Configure the IOMUX control register for 1-wire signals.
*/
iomux_config_mux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_pad(MX31_PIN_BATT_LINE, PAD_CTL_LOOPBACK);
}
/*!
* Setup GPIO for LCD to be inactive
*
*/
void gpio_lcd_inactive(void)
{
u16 pbc_bctrl1_set = 0;
/* RTS */
iomux_config_mux(AP_IPU_D2_CS, OUTPUTCONFIG_FUNC2, INPUTCONFIG_FUNC2);
pbc_bctrl1_set = (u16) PBC_BCTRL1_LCDON;
__raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET + 2);
}
void slcd_gpio_config(void)
{
gpio_config(2, 22, true, GPIO_INT_NONE);
gpio_set_data(2, 22, 1);
iomux_config_mux(AP_ED_INT4, OUTPUTCONFIG_DEFAULT, INPUTCONFIG_DEFAULT);
gpio_set_data(2, 22, 0);
msleep(100);
gpio_set_data(2, 22, 1);
msleep(100);
}
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param config a configuration as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config)
{
int ret = iomux_config_mux(pin, config);
int gpio = IOMUX_TO_GPIO(pin);
if (!ret && (gpio < MXC_GPIO_IRQS) && ((config == IOMUX_CONFIG_GPIO)
|| (config == PIN_TO_ALT_GPIO(pin)))) {
ret |= gpio_request(gpio, NULL);
}
return ret;
}
/*!
* Setup GPIO for FIRI port to be active
*/
void gpio_firi_active(void)
{
unsigned int pbc_bctrl1_set = 0;
/*
* IOMUX configs for Irda pins
*/
iomux_config_mux(PIN_IRDA_TX4, OUTPUTCONFIG_ALT2, INPUTCONFIG_NONE);
iomux_config_mux(PIN_IRDA_RX4, INPUTCONFIG_NONE, INPUTCONFIG_ALT2);
iomux_config_mux(PIN_GPIO6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
gpio_config(0, 6, true, GPIO_INT_NONE);
/* Clear the SD/Mode signal */
gpio_set_data(0, 6, 0);
/*
* Enable the Irda Transmitter
*/
pbc_bctrl1_set |= PBC_BCTRL1_IREN;
__raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET);
}
void slcd_gpio_config(void)
{
/* PIN_GPIO31 is actually bit 21 in in GPIO module!!! */
gpio_set_data(0, 21, 0);
gpio_config(0, 21, true, GPIO_INT_NONE);
iomux_config_mux(PIN_GPIO31, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
msleep(1);
gpio_set_data(0, 21, 1);
msleep(1);
}
/*!
* Setup GPIO for a CSPI device to be inactive
*
* @param cspi_mod a CSPI device
*/
void gpio_spi_inactive(int cspi_mod)
{
switch (cspi_mod) {
case 0:
/* SPI1_SS0 IOMux configuration */
iomux_config_mux(PIN_CSPI1_CS_0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI1 MISO IOMux configuration */
iomux_config_mux(PIN_CSPI1_DI, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI1 MOSI IOMux configuration */
iomux_config_mux(PIN_CSPI1_DO, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI1_SS1 IOMux configuration */
iomux_config_mux(PIN_CSPI1_CS_1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI1 CLK IOMux configuration */
iomux_config_mux(PIN_CSPI1_CK, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
break;
case 1:
/* SPI2_SS0 IOMux configuration */
iomux_config_mux(PIN_CSPI2_CS_0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI2 MISO IOMux configuration */
iomux_config_mux(PIN_CSPI2_DI, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI2 MOSI IOMux configuration */
iomux_config_mux(PIN_CSPI2_DO, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI2_SS1 IOMux configuration */
iomux_config_mux(PIN_CSPI2_CS_1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
/* SPI2 CLK IOMux configuration */
iomux_config_mux(PIN_CSPI2_CK, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
break;
default:
break;
}
}
/*!
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
*
* @param pin a name defined by \b iomux_pin_name_t
* @param cfg an input function as defined in \b #iomux_pin_cfg_t
*
* @return 0 if successful; Non-zero otherwise
*/
int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
{
int ret = iomux_config_mux(pin, cfg);
if (GPIO_TO_PORT(IOMUX_TO_GPIO(pin)) < GPIO_PORT_NUM) {
if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) ||
(((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) &&
((pin == MX35_PIN_GPIO1_0) || (pin == MX35_PIN_GPIO1_1) ||
(pin == MX35_PIN_GPIO2_0) || (pin == MX35_PIN_GPIO3_0))))
ret |= mxc_request_gpio(pin);
}
return ret;
}
/*!
* Setup the IOMUX/GPIO for SDHC1 SD1_DET.
*
* @param host Pointer to MMC/SD host structure.
* @param handler GPIO ISR function pointer for the GPIO signal.
* @return The function returns 0 on success and -1 on failure.
*
**/
int sdhc_intr_setup(void *host,
irqreturn_t(*handler) (int, void *, struct pt_regs *))
{
int ret;
/* MMC1_SDDET is connected to GPIO37 */
iomux_config_mux(PIN_GPIO37, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
/* check if a card in the slot if so we need to start with
* the proper edge definition
*/
sdhc_intr_clear(sdhc_find_card());
ret = request_irq(IOMUX_TO_IRQ(PIN_GPIO37), handler, 0, "MXCMMC", host);
return ret;
}
int mxc_iomux_gpio_mc13783_reset (void)
{
iomux_config_mux(PIN_USB_XRXD, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_TXENB, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
return 0;
}
/*!
* Setup GPIO for a CSPI device to be inactive
*
* @param cspi_mod a CSPI device
*/
void gpio_spi_inactive(int cspi_mod)
{
switch (cspi_mod) {
case 0:
/* SPI1_SS0 IOMux configuration */
iomux_config_mux(SP_SPI1_SS0, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI1 MISO IOMux configuration */
iomux_config_mux(SP_SPI1_MISO, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI1 MOSI IOMux configuration */
iomux_config_mux(SP_SPI1_MOSI, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI1_SS1 IOMux configuration */
iomux_config_mux(SP_SPI1_SS1, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI1 CLK IOMux configuration */
iomux_config_mux(SP_SPI1_CLK, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
break;
case 1:
/* SPI2 MOSI IOMux configuration */
iomux_config_mux(SP_SD2_CMD, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI2 SPI2_CLK IOMux configuration */
iomux_config_mux(SP_SD2_CLK, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI2 SPI2_MISO IOMux configuration */
iomux_config_mux(SP_SD2_DAT0, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* SPI2 SPI2_SS3 IOMux configuration */
iomux_config_mux(SP_SD2_DAT3, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
break;
default:
break;
}
}
/*!
* Setup the IOMUX/GPIO for SDHC1 SD1_DET.
*
* @param host Pointer to MMC/SD host structure.
* @param handler GPIO ISR function pointer for the GPIO signal.
* @return The function returns 0 on success and -1 on failure.
*
**/
int sdhc_intr_setup(void *host,
irqreturn_t(*handler) (int, void *, struct pt_regs *))
{
int ret;
/* use SD2_DAT1 as GPIO for SD1_DET */
iomux_config_mux(SP_SD2_DAT1, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_DEFAULT);
/* check if a card in the slot if so we need to start with
* the proper edge definition
*/
sdhc_intr_clear(sdhc_find_card());
ret = request_irq(IOMUX_TO_IRQ(SP_SD2_DAT1), handler,
0, "MXCMMC", host);
return ret;
}
/*! mxc_iomux_gpio_mc1383_set - set mc13783 iomux setting
* @param usb_mode
*/
int mxc_iomux_gpio_mc13783_set (int usb_mode)
{
printk (KERN_INFO"MXC gpio setting for Atlas\n");
printk(KERN_INFO"IOMUX setting for Argon+\n");
iomux_config_mux(PIN_USB_XRXD, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_TXENB, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
return 0;
}
int mxc_iomux_gpio_isp1301_set (struct otg_instance *otg, int usb_mode)
{
int gpio = 1;
printk (KERN_INFO"MXC gpio setting for isp1301\n");
isp1301_mod_init(otg, &zasevb_isp1301_bh);
TRACE_MSG0(otg->tcd->TAG, "5. IOMUX and GPIO Interrupt Configuration");
iomux_config_mux(PIN_GPIO2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
//Setting interrupt for ISP1301
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)
set_irq_type(IOMUX_TO_IRQ(PIN_GPIO2), IRQF_TRIGGER_FALLING);
#else
set_irq_type(IOMUX_TO_IRQ(PIN_GPIO2), IRQT_FALLING);
#endif
gpio = request_irq(IOMUX_TO_IRQ(PIN_GPIO2), zasevb_gpio_int_hndlr,
0, "ISP1301", (void *)&ocd_ops);
THROW_IF(gpio, error);
iomux_config_mux(PIN_USB_XRXD, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPOUT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VPIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_TXENB, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
iomux_config_mux(PIN_USB_VMIN, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
CATCH(error) {
printk(KERN_INFO"%s: failed\n", __FUNCTION__);
UNLESS (gpio) gpio_free_irq (ZGPIO_PORT, ZGPIO_PIN, GPIO_HIGH_PRIO);
return -EINVAL;
}
return 0;
}
/*!
* This function configures and drives a gpio to tell MC13783 to
* power down.
*/
void gpio_mc13783_power_off(void)
{
local_irq_disable();
/*
* Configure GPIO C15 as an output, as a GPIO, and as LOW.
* This is on the cpu schematic as XC_WDOG_AP_B, which is
* connected to the MC13783 WDI input pin. When MC13783 is in
* RUN mode, setting this line LOW will turn it off.
*/
/* Configure GPIO C15 as an output */
gpio_config(2, 15, true, GPIO_INT_NONE);
/* Configure GPIO C15 as a GPIO in the IOMUX */
iomux_config_mux(AP_GPIO_AP_C15, OUTPUTCONFIG_DEFAULT,
INPUTCONFIG_NONE);
/* Configure GPIO C15 as low */
gpio_set_data(2, 15, 0);
while (1) ;
}
int mxc_host_gpio (void)
{
iomux_config_mux(PIN_GPIO5, OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1); // USB1_OC
printk(KERN_INFO"%s: NONE/GPIO\n", __FUNCTION__);
return 0;
}
/*!
* Setup GPIO for SDHC1 to be inactive
*
* @param module SDHC module number
*/
void gpio_sdhc_inactive(int module)
{
unsigned int pbc_bctrl1_set = 0;
switch (module) {
case 0:
iomux_config_mux(PIN_MMC1_CLK, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC1_CMD, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC1_DATA_0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC1_DATA_1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC1_DATA_2, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC1_DATA_3, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
pbc_bctrl1_set &= PBC_BCTRL1_MCP1;
break;
case 1:
iomux_config_mux(PIN_MMC2_CLK, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC2_CMD, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC2_DATA_0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC2_DATA_1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC2_DATA_2, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_MMC2_DATA_3, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
pbc_bctrl1_set &= PBC_BCTRL1_MCP2;
break;
default:
break;
}
__raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET);
}
/*!
* Setup GPIO for a UART port to be active
*
* @param port a UART port
* @param no_irda indicates if the port is used for SIR
*/
void gpio_uart_active(int port, int no_irda)
{
unsigned int pbc_bctrl1_set = 0;
/*
* Configure the IOMUX control registers for the UART signals
*/
switch (port) {
/* UART 1 IOMUX Configs */
case 0:
if (no_irda == 1) {
iomux_config_mux(PIN_UART_TXD1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_RXD1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_RTS1_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_CTS1_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
/*
* Enable the UART 1 Transceiver
*/
pbc_bctrl1_set |= PBC_BCTRL1_UENA;
}
break;
/* UART 2 IOMUX Configs */
case 1:
if (no_irda == 1) {
iomux_config_mux(PIN_USB_VMOUT, OUTPUTCONFIG_ALT2, INPUTCONFIG_ALT2); /* TXD */
iomux_config_mux(PIN_USB_VPOUT, OUTPUTCONFIG_ALT2, INPUTCONFIG_ALT2); /* RXD */
iomux_config_mux(PIN_USB_XRXD, OUTPUTCONFIG_ALT1, INPUTCONFIG_ALT1); /* RTS */
iomux_config_mux(PIN_UART_CTS2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_DSR2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_DTR2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_RI2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_DCD2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
/*
* Enable the UART 2 Transceiver
*/
pbc_bctrl1_set |= PBC_BCTRL1_UENCE;
}
break;
/* UART 3 IOMUX Configs */
case 2:
if (no_irda == 1) {
iomux_config_mux(PIN_UART_TXD3, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_RXD3, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_RTS3_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_UART_CTS3_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
/*
* Enable the UART 3 Transceiver
*/
pbc_bctrl1_set |= PBC_BCTRL1_UENB;
}
break;
/*
* UART 4 IOMUX Configs
* UART 4 is used for Irda
*/
case 3:
if (no_irda == 0) {
/*
* IOMUX configs for Irda pins
*/
iomux_config_mux(PIN_IRDA_TX4, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
iomux_config_mux(PIN_IRDA_RX4, INPUTCONFIG_NONE,
INPUTCONFIG_FUNC);
iomux_config_mux(PIN_GPIO6, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
gpio_config(0, 6, true, GPIO_INT_NONE);
/* Clear the SD/Mode signal */
gpio_set_data(0, 6, 0);
/*
* Enable the Irda Transmitter
*/
pbc_bctrl1_set |= PBC_BCTRL1_IREN;
}
break;
default:
break;
}
__raw_writew(pbc_bctrl1_set, PBC_BASE_ADDRESS + PBC_BCTRL1_SET);
/*
* TODO: Configure the Pad registers for the UART pins
*/
}
/*!
* This function configures the MC13783 intrrupt operations.
*
*/
void gpio_mc13783_active(void *irq_handler)
{
iomux_config_mux(PIN_PM_INT, OUTPUTCONFIG_ALT2, INPUTCONFIG_ALT2);
// edio_config(ED_INT1, 0, EDIO_INT_RISE_EDGE);
}
/*!
* Setup GPIO for a keypad to be inactive
*/
void gpio_keypad_inactive(void)
{
iomux_config_mux(PIN_KEY_COL0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL2, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL4, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_COL7, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW0, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW2, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW3, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW4, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW6, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
iomux_config_mux(PIN_KEY_ROW7, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
}
