static void __init stmp378x_devb_init(void)
{
stmp3xxx_pinmux_init(NR_REAL_IRQS);
/* init stmp3xxx platform */
stmp3xxx_init();
/* Init iram allocate */
iram_init(STMP3XXX_OCRAM_PHBASE, STMP3XXX_OCRAM_SIZE);
stmp3xxx_dbguart.dev.platform_data = dbguart_pinmux;
stmp3xxx_appuart.dev.platform_data = appuart_pinmux;
stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
stmp3xxx_mmc.dev.platform_data = &mmc_data;
stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
stmp378x_i2c.dev.platform_data = &i2c_pins;
stmp3xxx_battery.dev.platform_data = &battery_data;
stmp3xxx_keyboard.dev.platform_data = &keyboard_data;
/* register spi devices */
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
/* add board's devices */
platform_add_devices(devices, ARRAY_SIZE(devices));
/* add devices selected by command line ssp1= and ssp2= options */
stmp3xxx_ssp1_device_register();
stmp3xxx_ssp2_device_register();
}
/*For MKD i490 HW Configuration: Reserved for future*/
static void __init mkd_i490_init_machine(void)
{
mx28_pinctrl_init();
/* Init iram allocate */
#ifdef CONFIG_VECTORS_PHY_ADDR
/* reserve the first page for irq vector table*/
iram_init(MX28_OCRAM_PHBASE + PAGE_SIZE, MX28_OCRAM_SIZE - PAGE_SIZE);
#else
iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE);
#endif
mx28_gpio_init();
mx28evk_pins_init();
mx28_device_init();
mx28evk_device_init();
}
/*!
* Post CPU init code
*
* @return 0 always
*/
static int __init post_cpu_init(void)
{
volatile unsigned long aips_reg;
iram_init(MX31_IRAM_BASE_ADDR, MX31_IRAM_SIZE);
/*
* S/W workaround: Clear the off platform peripheral modules
* Supervisor Protect bit for SDMA to access them.
*/
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
return 0;
}
static void __init imx233_olinuxino_init_machine(void)
{
mx23_pinctrl_init();
/* Init iram allocate */
#ifdef CONFIG_VECTORS_PHY_ADDR
/* reserve the first page for irq vectors table*/
iram_init(MX23_OCRAM_PHBASE + PAGE_SIZE, MX23_OCRAM_SIZE - PAGE_SIZE);
#else
iram_init(MX23_OCRAM_PHBASE, MX23_OCRAM_SIZE);
#endif
mx23_gpio_init();
imx233_olinuxino_pins_init();
mx23_device_init();
imx233_olinuxino_device_init();
}
static int __init post_cpu_init(void)
{
iram_init(MVF_IRAM_BASE_ADDR, MVF_IRAM_SIZE);
/* Move wait routine into iRAM */
ccm_base = MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR);
return 0;
}
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE);
base = ioremap(AIPS1_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
base = ioremap(AIPS2_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
if (enable_wait_mode) {
/* Allow SCU_CLK to be disabled when all cores are in WFI*/
base = IO_ADDRESS(SCU_BASE_ADDR);
reg = __raw_readl(base);
reg |= 0x20;
__raw_writel(reg, base);
}
/* Disable SRC warm reset to work aound system reboot issue */
base = IO_ADDRESS(SRC_BASE_ADDR);
reg = __raw_readl(base);
reg &= ~0x1;
__raw_writel(reg, base);
gpc_base = MX6_IO_ADDRESS(GPC_BASE_ADDR);
ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR);
num_cpu_idle_lock = 0x0;
init_mmdc_settings();
return 0;
}
/*!
* Post CPU init code
*
* @return 0 always
*/
static int __init post_cpu_init(void)
{
u32 reg;
void *l2_base;
volatile unsigned long aips_reg;
int iram_size = IRAM_SIZE;
#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE)
iram_size -= SCC_RAM_SIZE;
#endif
iram_init(IRAM_BASE_ADDR, iram_size);
gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K);
/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
reg = __raw_readl(MXC_ARM1176_BASE + 0x1C);
reg = 0x8;
__raw_writel(reg, MXC_ARM1176_BASE + 0x1C);
/* Initialize L2 cache */
l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
if (l2_base) {
l2x0_init(l2_base, 0x0003001B, 0x00000000);
}
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
return 0;
}
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
unsigned long iram_paddr, cpaddr;
iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE);
base = ioremap(AIPS1_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
base = ioremap(AIPS2_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
if (enable_wait_mode) {
/* Allow SCU_CLK to be disabled when all cores are in WFI*/
base = IO_ADDRESS(SCU_BASE_ADDR);
reg = __raw_readl(base);
reg |= 0x20;
__raw_writel(reg, base);
}
/* Disable SRC warm reset to work aound system reboot issue */
base = IO_ADDRESS(SRC_BASE_ADDR);
reg = __raw_readl(base);
reg &= ~0x1;
__raw_writel(reg, base);
/* Allocate IRAM for WAIT code. */
/* Move wait routine into iRAM */
cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr);
/* Need to remap the area here since we want the memory region
to be executable. */
mx6_wait_in_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
MT_MEMORY_NONCACHED);
pr_info("cpaddr = %x wait_iram_base=%x\n",
(unsigned int)cpaddr, (unsigned int)mx6_wait_in_iram_base);
/*
* Need to run the suspend code from IRAM as the DDR needs
* to be put into low power mode manually.
*/
memcpy((void *)cpaddr, mx6_wait, SZ_4K);
mx6_wait_in_iram = (void *)mx6_wait_in_iram_base;
gpc_base = MX6_IO_ADDRESS(GPC_BASE_ADDR);
ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR);
return 0;
}
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
u32 iram_size;
if (cpu_is_mx6q())
iram_size = MX6Q_IRAM_SIZE;
else
iram_size = MX6DL_MX6SL_IRAM_SIZE;
iram_init(MX6Q_IRAM_BASE_ADDR, iram_size);
base = ioremap(AIPS1_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
base = ioremap(AIPS2_ON_BASE_ADDR, PAGE_SIZE);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
/* Allow SCU_CLK to be disabled when all cores are in WFI*/
base = IO_ADDRESS(SCU_BASE_ADDR);
reg = __raw_readl(base);
reg |= 0x20;
__raw_writel(reg, base);
/* Disable SRC warm reset to work aound system reboot issue */
base = IO_ADDRESS(SRC_BASE_ADDR);
reg = __raw_readl(base);
reg &= ~0x1;
__raw_writel(reg, base);
gpc_base = MX6_IO_ADDRESS(GPC_BASE_ADDR);
ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR);
/* enable AXI cache for VDOA/VPU/IPU
* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
* clear OCRAM_CTL bits to disable pipeline control
*/
reg = __raw_readl(IOMUXC_GPR3);
reg &= ~IOMUXC_GPR3_OCRAM_CTL_EN;
__raw_writel(reg, IOMUXC_GPR3);
reg = __raw_readl(IOMUXC_GPR4);
reg |= IOMUXC_GPR4_VDOA_CACHE_EN | IOMUXC_GPR4_VPU_CACHE_EN |
IOMUXC_GPR4_IPU_CACHE_EN;
__raw_writel(reg, IOMUXC_GPR4);
__raw_writel(IOMUXC_GPR6_IPU1_QOS, IOMUXC_GPR6);
__raw_writel(IOMUXC_GPR7_IPU2_QOS, IOMUXC_GPR7);
num_cpu_idle_lock = 0x0;
if (cpu_is_mx6dl())
num_cpu_idle_lock = 0xffff0000;
#ifdef CONFIG_SMP
switch (setup_max_cpus) {
case 3:
num_cpu_idle_lock = 0xff000000;
break;
case 2:
num_cpu_idle_lock = 0xffff0000;
break;
case 1:
case 0:
num_cpu_idle_lock = 0xffffff00;
break;
}
#endif
/*
* The option to keep ARM memory clocks enabled during WAIT
* is only available on MX6SL, MX6DQ TO1.2 (or later) and
* MX6DL TO1.1 (or later)
* So if the user specifies "mem_clk_on" on any other chip,
* ensure that it is disabled.
*/
if (!cpu_is_mx6sl() && (mx6q_revision() < IMX_CHIP_REVISION_1_2) &&
(mx6dl_revision() < IMX_CHIP_REVISION_1_1))
mem_clk_on_in_wait = false;
if (cpu_is_mx6q())
chip_rev = mx6q_revision();
else if (cpu_is_mx6dl())
chip_rev = mx6dl_revision();
else
chip_rev = mx6sl_revision();
/* mx6sl doesn't have pcie. save power, disable PCIe PHY */
if (!cpu_is_mx6sl()) {
reg = __raw_readl(IOMUXC_GPR1);
reg = reg & (~IOMUXC_GPR1_PCIE_REF_CLK_EN);
reg |= IOMUXC_GPR1_TEST_POWERDOWN;
__raw_writel(reg, IOMUXC_GPR1);
}
return 0;
}
static int __init post_cpu_init(void)
{
void __iomem *base;
unsigned int reg;
struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk");
int iram_size = IRAM_SIZE;
if (!cpu_is_mx5())
return 0;
if (cpu_is_mx51()) {
mipi_hsc_disable();
#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE)
iram_size -= SCC_RAM_SIZE;
#endif
iram_init(MX51_IRAM_BASE_ADDR, iram_size);
} else {
iram_init(MX53_IRAM_BASE_ADDR, iram_size);
}
gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K);
ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K);
clk_enable(gpcclk);
/* Setup the number of clock cycles to wait for SRPG
* power up and power down requests.
*/
__raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR);
__raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR);
__raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR);
__raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR);
__raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR);
__raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR);
__raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR);
__raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR);
clk_disable(gpcclk);
clk_put(gpcclk);
/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K);
reg = 0x8;
__raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC);
base = ioremap(MX53_BASE_ADDR(AIPS1_BASE_ADDR), SZ_4K);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
base = ioremap(MX53_BASE_ADDR(AIPS2_BASE_ADDR), SZ_4K);
__raw_writel(0x0, base + 0x40);
__raw_writel(0x0, base + 0x44);
__raw_writel(0x0, base + 0x48);
__raw_writel(0x0, base + 0x4C);
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
iounmap(base);
if (cpu_is_mx51() || cpu_is_mx53()) {
/*Allow for automatic gating of the EMI internal clock.
* If this is done, emi_intr CCGR bits should be set to 11.
*/
base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K);
reg = __raw_readl(base + 0x8c);
reg &= ~0x1;
__raw_writel(reg, base + 0x8c);
iounmap(base);
}
if (cpu_is_mx50())
init_ddr_settings();
return 0;
}
