static int cuda_init(void)
{
if (sysinfo_get_value("cuda.address.physical", &(instance->cuda_physical)) != EOK)
return -1;
void *vaddr;
if (pio_enable((void *) instance->cuda_physical, sizeof(cuda_t), &vaddr) != 0)
return -1;
dev = vaddr;
instance->cuda = dev;
instance->xstate = cx_listen;
instance->bidx = 0;
instance->snd_bytes = 0;
fibril_mutex_initialize(&instance->dev_lock);
/* Disable all interrupts from CUDA. */
pio_write_8(&dev->ier, IER_CLR | ALL_INT);
cuda_irq_code.ranges[0].base = (uintptr_t) instance->cuda_physical;
cuda_irq_code.cmds[0].addr = (void *) &((cuda_t *) instance->cuda_physical)->ifr;
async_set_interrupt_received(cuda_irq_handler);
irq_register(10, device_assign_devno(), 0, &cuda_irq_code);
/* Enable SR interrupt. */
pio_write_8(&dev->ier, TIP | TREQ);
pio_write_8(&dev->ier, IER_SET | SR_INT);
/* Enable ADB autopolling. */
cuda_autopoll_set(true);
return 0;
}
void
notify_init(void)
{
irq_register(bp->intvec_notify, notify_irq);
notify_intvec = bp->intvec_notify;
}
/** Initializes and registers timer interrupt handler. */
static void icp_timer_irq_init(void)
{
irq_initialize(&icp.timer_irq);
icp.timer_irq.devno = device_assign_devno();
icp.timer_irq.inr = ICP_TIMER_IRQ;
icp.timer_irq.claim = icp_timer_claim;
icp.timer_irq.handler = icp_timer_irq_handler;
irq_register(&icp.timer_irq);
}
void irq_subscribe(uint8_t irq)
{
if (irq == 0) return;
Thread* current = scheduler_current();
if (!irqThread[irq])
{
irq_register(irq, irq_notify);
irqThread[irq] = current->tid;
}
}
void stm32_timer_init(CORE *core)
{
#if defined(STM32F1) || defined(STM32F2) || defined(STM32F4)
core->timer.shared1 = core->timer.shared8 = 0;
#endif
//setup HPET
irq_register(TIMER_VECTORS[HPET_TIMER], hpet_isr, (void*)core);
core->timer.hpet_uspsc = stm32_timer_get_clock(core, HPET_TIMER) / 1000000;
stm32_timer_open(core, HPET_TIMER, TIMER_ONE_PULSE | TIMER_IRQ_ENABLE | (13 << TIMER_IRQ_PRIORITY_POS));
CB_SVC_TIMER cb_svc_timer;
cb_svc_timer.start = hpet_start;
cb_svc_timer.stop = hpet_stop;
cb_svc_timer.elapsed = hpet_elapsed;
systime_hpet_setup(&cb_svc_timer, core);
#if !(STM32_RTC_DRIVER)
irq_register(TIMER_VECTORS[SECOND_PULSE_TIMER], second_pulse_isr, (void*)core);
stm32_timer_open(core, SECOND_PULSE_TIMER, TIMER_IRQ_ENABLE | (13 << TIMER_IRQ_PRIORITY_POS));
stm32_timer_start(core, SECOND_PULSE_TIMER, TIMER_VALUE_HZ, 1);
#endif //STM32_RTC_DRIVER
}
static inline void lpc_sdmmc_open(CORE* core, HANDLE user)
{
if (core->sdmmc.active)
{
error(ERROR_ALREADY_CONFIGURED);
return;
}
//enable SDIO bus interface to PLL1
LPC_CGU->BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD_Msk;
LPC_CGU->BASE_SDIO_CLK |= CGU_CLK_PLL1;
LPC_CGU->BASE_SDIO_CLK &= ~CGU_BASE_SDIO_CLK_PD_Msk;
//According to datasheet, we need to set SDDELAY here. But there is no SDDELAY register in CMSIS libs. WTF?
//reset bus, controller, DMA, FIFO
LPC_SDMMC->BMOD = SDMMC_BMOD_SWR_Msk;
LPC_SDMMC->CTRL = SDMMC_CTRL_CONTROLLER_RESET_Msk | SDMMC_CTRL_FIFO_RESET_Msk | SDMMC_CTRL_DMA_RESET_Msk ;
__NOP();
__NOP();
//mask and clear pending suspious interrupts
LPC_SDMMC->INTMASK = 0;
LPC_SDMMC->RINTSTS = 0x1ffff;
LPC_SDMMC->IDSTS = 0x337;
if (!sdmmcs_open(&core->sdmmc.sdmmcs))
return;
//it's critical to call malloc here, because of align
core->sdmmc.descr = malloc(LPC_SDMMC_DESCR_COUNT * sizeof(LPC_SDMMC_DESCR));
LPC_SDMMC->DBADDR = (unsigned int)(&(core->sdmmc.descr[0]));
LPC_SDMMC->BLKSIZ = core->sdmmc.sdmmcs.sector_size;
//recommended values
LPC_SDMMC->FIFOTH = (8 << SDMMC_FIFOTH_TX_WMARK_Pos) | (7 << SDMMC_FIFOTH_RX_WMARK_Pos) | SDMMC_FIFOTH_DMA_MTS_8;
//enable internal DMA
LPC_SDMMC->BMOD = SDMMC_BMOD_DE_Msk | SDMMC_BMOD_FB_Msk;
LPC_SDMMC->CTRL |= SDMMC_CTRL_USE_INTERNAL_DMAC_Msk;
//setup interrupt vector
irq_register(SDIO_IRQn, lpc_sdmmc_on_isr, (void*)core);
NVIC_EnableIRQ(SDIO_IRQn);
NVIC_SetPriority(SDIO_IRQn, 3);
//Enable interrupts
LPC_SDMMC->IDINTEN = SDMMC_IDINTEN_TI_Msk | SDMMC_IDINTEN_RI_Msk | SDMMC_IDINTEN_CES_Msk | SDMMC_IDINTEN_FBE_Msk |
SDMMC_IDINTEN_NIS_Msk | SDMMC_IDINTEN_AIS_Msk ;
//enable global interrupt mask
LPC_SDMMC->CTRL |= SDMMC_CTRL_INT_ENABLE_Msk;
core->sdmmc.user = user;
core->sdmmc.active = true;
}
// =====================================================================================================================
static int ps2_open(struct device* dev)
{
// allow only one endpoint to open the PS2 device
if (s_is_open)
return -1;
if (irq_register(PS2_IRQ, libdevman_server_get_port()) != 0)
return -1;
s_is_open = 1;
return 0;
}
struct irq_object * irq_object_create(unsigned irq)
{
if(irq_get_handler(irq) != 0)
return 0;
struct irq_object * retval = mm_allocate(sizeof(struct irq_object), MM_DEFAULT_ALIGNMENT,
MM_MEM_NORMAL);
retval->irq = irq;
retval->listener = 0;
irq_register(irq, irq_object_handler, retval);
return retval;
}
void ns16550_wire(ns16550_instance_t *instance, indev_t *input)
{
ASSERT(instance);
ASSERT(input);
instance->input = input;
irq_register(&instance->irq);
ns16550_clear_buffer(instance->ns16550);
/* Enable interrupts */
pio_write_8(&instance->ns16550->ier, IER_ERBFI);
pio_write_8(&instance->ns16550->mcr, MCR_OUT2);
}
static void raspberrypi_timer_irq_start(void)
{
/* Initialize timer IRQ */
static irq_t timer_irq;
irq_initialize(&timer_irq);
timer_irq.devno = device_assign_devno();
timer_irq.inr = BCM2835_TIMER1_IRQ;
timer_irq.claim = raspberrypi_timer_irq_claim;
timer_irq.handler = raspberrypi_timer_irq_handler;
irq_register(&timer_irq);
bcm2835_irc_enable(raspi.irc, BCM2835_TIMER1_IRQ);
bcm2835_timer_start(raspi.timer);
}
void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
{
cuda_t *dev = instance->cuda;
ASSERT(instance);
ASSERT(kbrdin);
instance->kbrdin = kbrdin;
irq_register(&instance->irq);
/* Enable SR interrupt. */
pio_write_8(&dev->ier, TIP | TREQ);
pio_write_8(&dev->ier, IER_SET | SR_INT);
/* Enable ADB autopolling. */
cuda_autopoll_set(instance, true);
}
void lpc_usb_open_device(CORE* core, HANDLE device)
{
int i;
core->usb.device = device;
lpc_pin_request_inside(core, HAL_REQ(HAL_PIN, IPC_OPEN), VBUS, PIO0_3_VBUS, 0);
#if (USB_SOFT_CONNECT)
lpc_pin_request_inside(core, HAL_REQ(HAL_PIN, IPC_OPEN), SCONNECT, PIO0_6_USB_CONNECT, 0);
#endif
//enable clock, power up
//power on. USBPLL must be turned on even in case of SYS PLL used. Why?
LPC_SYSCON->PDRUNCFG &= ~(SYSCON_PDRUNCFG_USBPLL_PD | SYSCON_PDRUNCFG_USBPAD_PD);
#if (USB_DEDICATED_PLL)
int i;
//enable and lock PLL
LPC_SYSCON->USBPLLCTRL = ((USBPLL_M - 1) << SYSCON_USBPLLCTRL_MSEL_POS) | ((32 - __builtin_clz(USBPLL_P)) << SYSCON_USBPLLCTRL_PSEL_POS);
LPC_SYSCON->USBPLLCLKSEL = SYSCON_USBPLLCLKSEL_SYSOSC;
LPC_SYSCON->USBPLLCLKUEN = 0;
LPC_SYSCON->USBPLLCLKUEN = SYSCON_SYSPLLCLKUEN_ENA;
//wait for PLL lock
for (i = 0; i < PLL_LOCK_TIMEOUT; ++i)
{
if (LPC_SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK)
break;
}
LPC_SYSCON->USBCLKSEL = SYSCON_USBCLKSEL_PLL;
#else
LPC_SYSCON->USBCLKSEL = SYSCON_USBCLKSEL_MAIN;
#endif
//switch to clock source
LPC_SYSCON->USBCLKUEN = 0;
LPC_SYSCON->USBCLKUEN = SYSCON_USBCLKUEN_ENA;
//turn clock on
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << SYSCON_SYSAHBCLKCTRL_USB_POS) | (1 << SYSCON_SYSAHBCLKCTRL_USBRAM_POS);
//clear any spurious pending interrupts
LPC_USB->DEVCMDSTAT = USB_DEVCMDSTAT_DCON_C | USB_DEVCMDSTAT_DSUS_C | USB_DEVCMDSTAT_DRES_C | USB_DEVCMDSTAT_SETUP;
LPC_USB->INTSTAT = USB_INTSTAT_EP0OUT | USB_INTSTAT_EP0IN | USB_INTSTAT_EP1OUT | USB_INTSTAT_EP1IN |
USB_INTSTAT_EP2OUT | USB_INTSTAT_EP2IN | USB_INTSTAT_EP3OUT | USB_INTSTAT_EP3IN |
USB_INTSTAT_EP4OUT | USB_INTSTAT_EP4IN | USB_INTSTAT_FRAME_INT | USB_INTSTAT_DEV_INT;
#if (USB_DEBUG_ERRORS)
LPC_USB->INFO &= ~USB_INFO_ERR_CODE_MASK;
#endif
//setup buffer descriptor table
LPC_USB->EPLISTSTART = USB_RAM_BASE & ~0xff;
LPC_USB->DATABUFSTART = USB_BUF_BASE & ~0x3fffff;
//clear descriptor table data
for (i = 0; i < USB_HW_EP_COUNT; ++i)
{
*USB_EP_LISTSTS(i, 0) = *USB_EP_LISTSTS(i, 1) = 0;
*USB_EP_LISTSTS(i | USB_EP_IN, 0) = *USB_EP_LISTSTS(i | USB_EP_IN, 1) = 0;
}
//SETUP buffer offset is not incremented
*USB_EP_LISTSTS(0, 1) = USB_EP_LISTST_OFFSET_SET(USB_SETUP_BUF_BASE);
//enable interrupts
irq_register(USB_IRQn, lpc_usb_on_isr, core);
NVIC_EnableIRQ(USB_IRQn);
NVIC_SetPriority(USB_IRQn, 1);
//Unmask common interrupts
LPC_USB->INTEN = USB_INTSTAT_DEV_INT;
#if (USB_SOFT_CONNECT)
//pullap
LPC_USB->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON;
#endif
}
/** Register a new PCI ATA channel.
* @param pci_device PCI device the channel is on.
* @param idx Channel index.
* @param ctrl_base Control registers base address.
* @param cmd_base Command registers base address.
* @param bm_base Bus master base address.
* @param irq IRQ number.
* @return Pointer to ATA channel structure if present. */
static ata_channel_t *pci_ata_channel_add(pci_device_t *pci_device, int idx, uint32_t ctrl_base,
uint32_t cmd_base, uint32_t bm_base, uint32_t irq) {
uint16_t pci_cmd_old, pci_cmd_new;
pci_ata_channel_t *channel;
bool dma = true;
status_t ret;
/* Configure the PCI device appropriately. */
pci_cmd_old = pci_cmd_new = pci_config_read16(pci_device, PCI_CONFIG_COMMAND);
pci_cmd_new &= ~PCI_COMMAND_INT_DISABLE;
pci_cmd_new |= (PCI_COMMAND_IO | PCI_COMMAND_BUS_MASTER);
if(pci_cmd_new != pci_cmd_old) {
pci_config_write16(pci_device, PCI_CONFIG_COMMAND, pci_cmd_new);
kprintf(LOG_DEBUG, "ata: reconfigured PCI device %d:%02x.%d (old: 0x%04x, new: 0x%04x)\n",
pci_device->bus, pci_device->device, pci_device->function,
pci_cmd_old, pci_cmd_new);
}
/* Check presence by writing a value to the low LBA port on the channel,
* then reading it back. If the value is the same, it is present. */
out8(cmd_base + ATA_CMD_REG_LBA_LOW, 0xAB);
if(in8(cmd_base + ATA_CMD_REG_LBA_LOW) != 0xAB) {
if(pci_cmd_new != pci_cmd_old) {
pci_config_write16(pci_device, PCI_CONFIG_COMMAND, pci_cmd_old);
}
return NULL;
}
/* Allocate our information structure. */
channel = kmalloc(sizeof(*channel), MM_WAIT);
channel->channel = NULL;
channel->pci_device = pci_device;
channel->ctrl_base = ctrl_base;
channel->cmd_base = cmd_base;
channel->bus_master_base = bm_base + (idx * 8);
channel->irq = irq;
channel->prdt = NULL;
/* If the bus master is in simplex mode, disable DMA on the second
* channel. According to the Haiku code, Intel controllers use this for
* something other than simplex mode. */
if(pci_device->vendor_id != 0x8086) {
if(in8(bm_base + PCI_ATA_BM_REG_STATUS) & PCI_ATA_BM_STATUS_SIMPLEX && idx > 1) {
dma = false;
}
}
/* Allocate a PRDT if necessary. */
if(dma) {
phys_alloc(PRDT_SIZE, 0, 0, 0, (phys_ptr_t)0x100000000, MM_WAIT, &channel->prdt_phys);
channel->prdt = phys_map(channel->prdt_phys, PRDT_SIZE, MM_WAIT);
}
/* Register the IRQ handler. */
ret = irq_register(channel->irq, pci_ata_irq_handler, NULL, channel);
if(ret != STATUS_SUCCESS) {
kprintf(LOG_WARN, "ata: failed to register PCI ATA IRQ handler %u\n", channel->irq);
if(dma) {
phys_unmap(channel->prdt, PRDT_SIZE, true);
phys_free(channel->prdt_phys, PRDT_SIZE);
}
kfree(channel);
return NULL;
}
/* Try to register the ATA channel. */
channel->channel = ata_sff_channel_add(pci_device->node, idx, &pci_ata_channel_ops, channel,
dma, PRDT_ENTRIES, (phys_ptr_t)0x100000000);
if(!channel->channel) {
irq_unregister(channel->irq, pci_ata_irq_handler, NULL, channel);
if(dma) {
phys_unmap(channel->prdt, PRDT_SIZE, true);
phys_free(channel->prdt_phys, PRDT_SIZE);
}
kfree(channel);
return NULL;
}
return channel->channel;
}
// =====================================================================================================================
void sched_arch_init()
{
irq_register(0, sched_irq, NULL);
}
static __init void realview_irq_init(void)
{
u32_t i;
u32_t max_irq;
u32_t cpumask;
/* get cpumask */
cpumask = 1 << 0;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
/* ignore all peripheral interrupt signals */
writel(REALVIEW_GIC1_DIST_CTRL, 0);
/*
* find out how many interrupts are supported.
* and the GIC only supports up to 1020 interrupt sources.
*/
max_irq = readl(REALVIEW_GIC1_DIST_CTR) & 0x1f;
max_irq = (max_irq + 1) * 32;
if(max_irq > 1020)
max_irq = 1020;
/*
* set all global interrupts to be level triggered, active low.
*/
for(i = 32; i < max_irq; i += 16)
writel(REALVIEW_GIC1_DIST_CONFIG + i * 4 / 16, 0);
/*
* set all global interrupts to this CPU only.
*/
for(i = 32; i < max_irq; i += 4)
writel(REALVIEW_GIC1_DIST_TARGET + i * 4 / 4, cpumask);
/*
* set priority on all interrupts.
*/
for(i = 0; i < max_irq; i += 4)
writel(REALVIEW_GIC1_DIST_PRI + i * 4 / 4, 0xa0a0a0a0);
/*
* disable all interrupts.
*/
for(i = 0; i < max_irq; i += 32)
writel(REALVIEW_GIC1_DIST_ENABLE_CLEAR + i * 4 / 32, 0xffffffff);
/* monitor the peripheral interrupt signals */
writel(REALVIEW_GIC1_DIST_CTRL, 1);
/* the priority mask level for cpu interface */
writel(REALVIEW_GIC1_CPU_PRIMASK, 0xf0);
/* enable signalling of interrupts */
writel(REALVIEW_GIC1_CPU_CTRL, 1);
/* initial irq's handler to null_irq_handler */
for(i = 0; i < ARRAY_SIZE(realview_irq_handler); i++)
{
realview_irq_handler[i] = (irq_handler)null_irq_handler;
}
for(i = 0; i < ARRAY_SIZE(realview_irqs); i++)
{
if(!irq_register(&realview_irqs[i]))
{
LOG_E("failed to register irq '%s'", realview_irqs[i].name);
}
}
/* enable irq and fiq */
irq_enable();
fiq_enable();
}
