void uart_init(uint8_t uart, uint8_t interrupts)
{
uint8_t irq = uart2irq[uart];
uart_reg_write(uart, IER, 0x00);
if (uart == cons_get_uart()) {
cons_init();
if(interrupts) {
irq_register_handler(irq, &uart_irq_handler_cons);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
} else if (uart == sercomm_get_uart()) {
sercomm_init();
if(interrupts) {
irq_register_handler(irq, &uart_irq_handler_sercomm);
irq_config(irq, 0, 0, 0xff);
irq_enable(irq);
}
uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
} else {
return;
}
#if 0
if (uart == 1) {
/* assign UART to MCU and unmask interrupts*/
writeb(UART_REG_UIR, 0x00);
}
#endif
/* if we don't initialize these, we get strange corruptions in the
received data... :-( */
uart_reg_write(uart, MDR1, 0x07); /* turn off UART */
uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */
uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
/* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
uart_reg_write(uart, EFR, (1 << 4));
/* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */
uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
(3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT));
/* THR interrupt only when TX FIFO and TX shift register are empty */
uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));
/* 8 bit, 1 stop bit, no parity, no break */
uart_reg_write(uart, LCR, 0x03);
uart_set_lcr7bit(uart, 0);
}
/*! \brief Starts the ABDAC.
* \param sample_rate_hz Sample rate for the ABDAC.
* \param num_channels number of channel
* \param bits_per_sample number of bit per sample
* \param swap_channels true -> swap the channels
* \param callback Provide a functions that handles callback.
* \param callback_opt Callback flag
* \param pba_hz Speed of the peripheral bus A.
*/
void tpa6130_dac_start(uint32_t sample_rate_hz,
uint8_t num_channels,
uint8_t bits_per_sample,
bool swap_channels,
void (*callback)(uint32_t arg),
uint32_t callback_opt,
uint32_t pba_hz)
{
/* stop ABDAC if running*/
tpa6130_dac_stop();
/* configure used pins for ABDAC */
gpio_enable_module(TPA6130_ABDAC_GPIO_MAP,
sizeof(TPA6130_ABDAC_GPIO_MAP) /
sizeof(TPA6130_ABDAC_GPIO_MAP[0]));
/* configure and start PDC and ABDAC*/
tpa6130_dac_setup(sample_rate_hz,
num_channels,
bits_per_sample,
swap_channels,
callback,
callback_opt,
pba_hz);
/* Register a interrupt service routine for the ABDAC channel of
* the PDCA
*/
irq_register_handler(tpa6130_abdac_tx_pdca_int_handler, TPA6130_ABDAC_PDCA_IRQ, 1);
tpa6130_powerup();
}
void twl3025_init(void)
{
spi_init();
twl3025_switch_page(0);
twl3025_clk13m(1);
twl3025_reg_write(AFCCTLADD, 0x01); /* AFCCK(1:0) must not be zero! */
twl3025_unit_enable(TWL3025_UNIT_AFC, 1);
irq_register_handler(IRQ_EXTERNAL, &twl3025_irq);
irq_config(IRQ_EXTERNAL, 0, 0, 0);
irq_enable(IRQ_EXTERNAL);
irq_register_handler(IRQ_EXTERNAL_FIQ, &twl3025_irq);
irq_config(IRQ_EXTERNAL_FIQ, 1, 0, 0);
irq_enable(IRQ_EXTERNAL_FIQ);
}
/**
* \brief Set callback for given EIC line
*
* \param [in] eic Base address of the EIC module
* \param [in] line_number Number of line
* \param [in] callback Callback function pointer
* \param [in] irq_line Interrupt line number (EIC_1_IRQn to EIC_8_IRQn)
* \param [in] irq_level Interrupt level (the priority of the interrupt request)
*/
void eic_line_set_callback(Eic *eic, uint8_t line_number,
eic_callback_t callback, uint8_t irq_line, uint8_t irq_level)
{
eic_callback_pointer[line_number] = callback;
irq_register_handler((IRQn_Type)irq_line, irq_level);
eic_line_enable_interrupt(eic, line_number);
}
int twi_master_init(volatile avr32_twi_t *twi, const twi_options_t *opt)
{
irqflags_t flags = sysreg_read(AVR32_SR);
int status = TWI_SUCCESS;
// Set pointer to TWIM instance for IT
twi_inst = twi;
// Disable TWI interrupts
cpu_irq_disable();
twi->idr = ~0UL;
twi->sr;
// Reset TWI
twi->cr = AVR32_TWI_CR_SWRST_MASK;
cpu_irq_restore(flags);
// Dummy read in SR
twi->sr;
// register Register twim_master_interrupt_handler interrupt
// on level CONF_TWI_IRQ_LEVEL
flags = cpu_irq_save();
irq_register_handler(&twi_master_interrupt_handler, CONF_TWI_IRQ_LINE,
CONF_TWI_IRQ_LEVEL);
cpu_irq_restore(flags);
// Select the speed
twi_set_speed(twi, opt->speed, opt->pba_hz);
// Probe the component
//status = twi_probe(twi, opt->chip);
return status;
}
/**
* \brief Set callback for AES
*
* \param dev_inst Device structure pointer.
* \param source Interrupt source.
* \param callback callback function pointer.
* \param irq_level interrupt level.
*/
void aes_set_callback(struct aes_dev_inst *const dev_inst,
aes_interrupt_source_t source, aes_callback_t callback,
uint8_t irq_level)
{
aes_callback_pointer = callback;
irq_register_handler((IRQn_Type)AESA_IRQn, irq_level);
aes_enable_interrupt(dev_inst, source);
}
/**
* \brief Set callback for FREQM interrupt handler
*
* \param dev_inst Device structure pointer.
* \param source Interrupt source.
* \param callback callback function pointer.
* \param irq_level interrupt level.
*/
void freqm_set_callback(struct freqm_dev_inst *const dev_inst,
freqm_interrupt_source_t source, freqm_callback_t callback,
uint8_t irq_level)
{
freqm_callback[source] = callback;
irq_register_handler((IRQn_Type)FREQM_IRQn, irq_level);
freqm_enable_interrupt(dev_inst, source);
}
/**
* \brief Set callback for ADC
*
* \param dev_inst Device structure pointer.
* \param source interrupt source.
* \param callback callback function pointer.
* \param irq_line interrupt line.
* \param irq_level interrupt level.
*/
void adc_set_callback(struct adc_dev_inst *const dev_inst,
adc_interrupt_source_t source, adc_callback_t callback,
uint8_t irq_line, uint8_t irq_level)
{
adc_callback_pointer = callback;
irq_register_handler((IRQn_Type) irq_line, irq_level);
adc_enable_interrupt(dev_inst, source);
}
/**
* \brief Set callback for AC
*
* \param dev_inst Device structure pointer
* \param source Interrupt source
* \param callback Callback function pointer
* \param irq_level Interrupt level
*/
void ac_set_callback(struct ac_dev_inst *const dev_inst,
ac_interrupt_source_t source, ac_callback_t callback,
uint8_t irq_level)
{
ac_callback_pointer[source] = callback;
irq_register_handler(ACIFC_IRQn, irq_level);
ac_enable_interrupt(dev_inst, source);
}
void init_timer() {
uint32_t divisor = TIMER_QUOTIENT / TIMER_FREQ;
outportb(PIT_CMD, PIT_SET);
outportb(PIT_0, divisor & 0xFF);
outportb(PIT_0, (divisor >> 8) & 0xFF);
irq_register_handler(IRQ0, &timer_callback);
}
/**
* \brief Set callback for given PDCA channel
*
* \param pdca_ch_number PDCA channel number
* \param callback callback function pointer
* \param irq_line interrupt line.
* \param irq_level interrupt level.
* \param pdca_channel_interrupt_mask Interrupts to be enabled.
*/
void pdca_channel_set_callback(pdca_channel_num_t pdca_ch_number,
pdca_callback_t callback, uint8_t irq_line, uint8_t irq_level,
const pdca_channel_interrupt_mask_t pdca_channel_interrupt_mask)
{
pdca_callback_pointer[pdca_ch_number] = callback;
irq_register_handler((IRQn_Type) irq_line, irq_level);
pdca_channel_enable_interrupt(pdca_ch_number,
pdca_channel_interrupt_mask);
}
/* Initialize simcard interface */
void calypso_sim_init(void)
{
/* Register IRQ handler and turn interrupts on */
#if (SIM_DEBUG == 1)
puts("SIM: Registering interrupt handler for simcard-interface\n");
#endif
irq_register_handler(IRQ_SIMCARD, &sim_irq_handler);
irq_config(IRQ_SIMCARD, 0, 0, 0xff);
irq_enable(IRQ_SIMCARD);
}
/**
* \brief Set callback for ADC
*
* \param adc Base address of the ADC
* \param source Interrupt source
* \param callback Callback function pointer
* \param irq_level Interrupt level
*/
void adc_set_callback(Adc *const adc, enum adc_interrupt_source source,
adc_callback_t callback, uint8_t irq_level)
{
Assert(adc);
Assert(callback);
adc_callback_pointer[source] = callback;
irq_register_handler(ADC_IRQn, irq_level);
/* Enable the specified interrupt source */
adc_enable_interrupt(adc, source);
}
/**
* \brief Touch Library & Sensors Intialization
* - Register the CAT interrupt with priority level 3
* - Initialize the touch library
* - Intilialize the Autonomous touch sensor
*
* \retval STATUS_OK Configuration success
* \retval ERR_INVALID_ARG Error in configuration parameters
*/
static status_code_t touch_api_init()
{
touch_ret_t touch_ret = TOUCH_SUCCESS;
/* Enable CAT PBA clock */
sysclk_enable_pba_module(SYSCLK_CAT);
/* Disable global interrupts */
cpu_irq_disable();
/*
* Initialize the interrupt vectors
* Note: This function does nothing for IAR as the interrupts are
*handled
* by the IAR compiler itself. It provides an abstraction between GCC &
* IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_initialize_vectors();
/*
* Register the Touch Library CAT interrupt handler to the interrupt
* controller.
* Note: The Touch Library CAT interrupt level for the case
* of IAR is fixed to Interrupt level 3. This function does nothing for
* IAR as the interrupts are handled by the IAR compiler itself. It
* provides an abstraction between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_register_handler(&touch_acq_done_irq, AVR32_CAT_IRQ, 3);
/* Enable global interrupt */
cpu_irq_enable();
/* Initialize touch library and CAT module for Autonomous QTouch
* operation. */
touch_ret = touch_at_sensor_init(&touch_config);
/* Check API Error return code. */
if (touch_ret != TOUCH_SUCCESS) {
return ERR_INVALID_ARG;
}
/*
* Enable Autonomous QTouch sensor for continuous acquisition. IN_TOUCH
* or OUT_OF_TOUCH status is continuously updated until the sensor is
* disabled using the touch_at_sensor_disable() API.
*/
touch_ret
= touch_at_sensor_enable(touch_at_status_change_interrupt_callback);
/* Check API Error return code. */
if (touch_ret != TOUCH_SUCCESS) {
return ERR_INVALID_ARG;
}
return STATUS_OK;
} /* End of touch_api_init() */
/**
* \brief Set callback for AES
*
* \param p_aes Base address of the AES instance.
* \param source Interrupt source.
* \param callback callback function pointer.
* \param irq_level interrupt level.
*/
void aes_set_callback(Aes *const p_aes,
aes_interrupt_source_t source, aes_callback_t callback,
uint8_t irq_level)
{
if (source == AES_INTERRUPT_DATA_READY) {
aes_callback_pointer[0] = callback;
} else if (source == AES_INTERRUPT_UNSPECIFIED_REGISTER_ACCESS) {
aes_callback_pointer[1] = callback;
}
irq_register_handler((IRQn_Type)AES_IRQn, irq_level);
aes_enable_interrupt(p_aes, source);
}
/**
* \brief Set callback for TWIS
*
* \note Slave address match interrupt is enabled in default so that TWIS ISR
* can work appropriately.
*
* \param dev_inst Device structure pointer
* \param source Interrupt source
* \param callback Callback function pointer
* \param irq_level Interrupt level
*/
void twis_set_callback(struct twis_dev_inst *const dev_inst,
twis_interrupt_source_t source, twis_callback_t callback,
uint8_t irq_level)
{
Assert(dev_inst);
Assert(dev_inst->hw_dev);
Assert(callback);
uint32_t i = twis_find_ch_num(dev_inst->hw_dev);
twis_callback_pointer[i] = callback;
if (!i) {
irq_register_handler(TWIS0_IRQn, irq_level);
} else if (i == 1) {
irq_register_handler(TWIS1_IRQn, irq_level);
}
/* Enable the specified interrupt source */
twis_enable_interrupt(dev_inst, source);
/* Enable slave address match interrupt in default */
if (source != TWIS_INTERRUPT_SLAVEADR_MATCH) {
twis_enable_interrupt(dev_inst, TWIS_INTERRUPT_SLAVEADR_MATCH);
}
}
static void ui_button_rtc_init(void)
{
irq_register_handler(button_rtc_irq, BUTTON_RTC_IRQ,
BUTTON_RTC_IRQ_PRIORITY);
rtc_init(&AVR32_RTC, RTC_OSC_32KHZ, 7);
rtc_set_top_value(&AVR32_RTC, 0);
rtc_enable_interrupt(&AVR32_RTC);
rtc_enable(&AVR32_RTC);
}
void keypad_init(uint8_t interrupts)
{
lastbuttons = 0;
polling = 0;
writew(0, KBD_GPIO_MASKIT);
writew(0, KBC_REG);
if(interrupts) {
with_interrupts = 1;
irq_register_handler(IRQ_KEYPAD_GPIO, &keypad_irq);
irq_config(IRQ_KEYPAD_GPIO, 0, 0, 0);
irq_enable(IRQ_KEYPAD_GPIO);
}
}
/* timer4 is use as system timer */
void sys_timer_init(unsigned int interval_ms)
{
TCON_REG &= ~(1<<20);//stop timer4
TCFG0_REG &= ~(0xff << 8);
TCFG0_REG |= (0x01 << 8); //prescaler:1 => freq:pclk/2
TCFG1_REG &= ~(0xf << 16); //divider:1
TCON_REG |= (1<<21) | (1<<22); // auto_reload,update TCNTB4
TCNTB4_REG = (pclk/2)/1000*interval_ms; //10ms
irq_register_handler(IRQ_TIMER4_VIC, SYS_TIMER_PRIO, sys_timer_irq);
}
void intc_init_module(void)
{
int i;
saved_intc_mask = 0;
*intc_mask = *intc_mask;
*intc_stat = *intc_stat;
for (i = 0; i < INTC_NUMBER_OF_HANDLERS; i++) {
intc_handler[i] = NULL;
}
/* Register an interrupt handler. */
irq_register_handler(IRQ_IM2, intc_interrupt);
}
static void ui_display_init_rtc(void)
{
irq_register_handler(display_rtc_irq, DISPLAY_RTC_IRQ,
DISPLAY_RTC_IRQ_PRIORITY);
rtc_init(&AVR32_RTC, RTC_OSC_32KHZ, RTC_PSEL_32KHZ_1HZ - 1);
rtc_enable_wake_up(&AVR32_RTC);
rtc_set_top_value(&AVR32_RTC, 0);
rtc_enable_interrupt(&AVR32_RTC);
rtc_enable(&AVR32_RTC);
}
/**
* \brief Initialize the twi master module
*
* \param twim Base address of the TWIM (i.e. &AVR32_TWIM)
* \param *opt Options for initializing the twim module
* (see \ref twim_options_t)
* \retval STATUS_OK Transaction is successful
* \retval ERR_INVALID_ARG Invalid arg resulting in wrong CWGR Exponential
* \retval ERR_IO_ERROR NACK is received or Bus Arbitration lost
*/
status_code_t twim_master_init (volatile avr32_twim_t *twim,
const twim_options_t *opt)
{
bool global_interrupt_enabled = cpu_irq_is_enabled ();
// Initialize bus transfer status
transfer_status = TWI_SUCCESS;
// Disable TWI interrupts
if (global_interrupt_enabled) {
cpu_irq_disable ();
}
twim->idr = ~0UL;
// Enable master transfer
twim->cr = AVR32_TWIM_CR_MEN_MASK;
// Reset TWI
twim->cr = AVR32_TWIM_CR_SWRST_MASK;
if (global_interrupt_enabled) {
cpu_irq_enable ();
}
// Clear SR
twim->scr = ~0UL;
// register Register twim_master_interrupt_handler interrupt on level CONF_TWIM_IRQ_LEVEL
irqflags_t flags = cpu_irq_save();
irq_register_handler(twim_master_interrupt_handler,
CONF_TWIM_IRQ_LINE, CONF_TWIM_IRQ_LEVEL);
cpu_irq_restore(flags);
/*
if (opt->smbus) {
// Enable SMBUS Transfer
twim->cr = AVR32_TWIM_CR_SMEN_MASK;
twim->smbtr = (uint32_t) -1;
}
*/
// Select the speed
if (twim_set_speed (twim, opt->speed, opt->pba_hz) ==
ERR_INVALID_ARG) {
return ERR_INVALID_ARG;
}
// Probe the component
twim_probe (twim, opt->chip);
//Check for nack and abitration
if (transfer_status == TWI_RECEIVE_NACK
|| transfer_status == TWI_ARBITRATION_LOST) {
return ERR_IO_ERROR;
}
return STATUS_OK;
}
int twi_slave_init(volatile avr32_twi_t *twi, const twi_options_t *opt,
const twi_slave_fct_t *slave_fct)
{
irqflags_t flags = sysreg_read(AVR32_SR);
// Set pointer to TWIM instance for IT
twi_inst = twi;
// Disable TWI interrupts
cpu_irq_disable();
twi->idr = ~0UL;
twi->sr;
// Reset TWI
twi->cr = AVR32_TWI_CR_SWRST_MASK;
cpu_irq_restore(flags);
// Dummy read in SR
twi->sr;
// register Register twim_master_interrupt_handler interrupt
// on level CONF_TWI_IRQ_LEVEL
flags = cpu_irq_save();
irq_register_handler(&twi_slave_interrupt_handler, CONF_TWI_IRQ_LINE,
CONF_TWI_IRQ_LEVEL);
cpu_irq_restore(flags);
// Set slave address
twi->smr = (opt->chip << AVR32_TWI_SMR_SADR_OFFSET);
// Disable master transfer
twi->cr = AVR32_TWI_CR_MSDIS_MASK;
// Enable slave
twi->cr = AVR32_TWI_CR_SVEN_MASK;
// get a pointer to applicative routines
twi_slave_fct = *slave_fct;
// Slave Access Interrupt Enable
twi_it_mask = AVR32_TWI_IER_SVACC_MASK;
twi->ier = twi_it_mask;
// Everything went ok
return TWI_SUCCESS;
}
void icm_set_callback(Icm *p_icm, icm_callback_t callback,
enum icm_region_num reg_num, enum icm_interrupt_source interrupt_source,
uint8_t irq_level)
{
Assert(p_icm);
Assert(callback);
icm_callback_pointer[interrupt_source] = callback;
irq_register_handler(ICM_IRQn, irq_level);
if(interrupt_source == ICM_INTERRUPT_URAD) {
icm_enable_interrupt(p_icm,
1 << (uint32_t)(_ICM_NUM_OF_REGION * (uint32_t)interrupt_source));
} else {
icm_enable_interrupt(p_icm,
1 << (_ICM_NUM_OF_REGION * (uint32_t)interrupt_source + reg_num));
}
}
/*! \brief Enable an EIC interrupt line.
*
* This routine maps a GPIO pin and peripheral function to a specified EIC line.
*
* \param eic_line Line number to enable
* \param eic_pin GPIO module pin
* \param eic_func GPIO module function
* \param eic_irq IRQ of the interrupt handler
* \param eic_handler Interrupt handler to register
*/
static void eic_irq_connect(uint32_t eic_line, uint32_t eic_pin,
uint32_t eic_func, uint32_t eic_irq, __int_handler eic_handler)
{
eic_options_t const eic_options = {
.eic_line = eic_line,
.eic_mode = EIC_MODE_EDGE_TRIGGERED,
.eic_edge = EIC_EDGE_RISING_EDGE,
.eic_level = EIC_LEVEL_HIGH_LEVEL,
.eic_filter = EIC_FILTER_ENABLED,
.eic_async = EIC_ASYNCH_MODE
};
sysclk_enable_pba_module(SYSCLK_EIC);
gpio_enable_module_pin(eic_pin, eic_func);
irq_register_handler(eic_handler, eic_irq, 0);
eic_init(&AVR32_EIC, &eic_options, 1);
eic_enable_line(&AVR32_EIC, eic_line);
eic_enable_interrupt_line(&AVR32_EIC, eic_line);
}
/*! \brief to register the timer callback with the corresponding handler ID
*/
static void configure_irq_handler(void)
{
if (&AVR32_TC0 == TIMER) {
switch (TIMER_CHANNEL_ID) {
case 0:
irq_register_handler(tc0_callback, AVR32_TC0_IRQ0,
TIMER_CHANNEL_ID);
break;
case 1:
irq_register_handler(tc0_callback, AVR32_TC0_IRQ1,
TIMER_CHANNEL_ID);
break;
case 2:
irq_register_handler(tc0_callback, AVR32_TC0_IRQ2,
TIMER_CHANNEL_ID);
break;
default:
break;
}
}
if (&AVR32_TC1 == TIMER) {
switch (TIMER_CHANNEL_ID) {
case 0:
irq_register_handler(tc1_callback, AVR32_TC1_IRQ0,
TIMER_CHANNEL_ID);
break;
case 1:
irq_register_handler(tc1_callback, AVR32_TC1_IRQ1,
TIMER_CHANNEL_ID);
break;
case 2:
irq_register_handler(tc1_callback, AVR32_TC1_IRQ2,
TIMER_CHANNEL_ID);
break;
default:
break;
}
}
}
void setup_timeoutcnt(void)
{
sysclk_enable_peripheral_clock(ID_TC0);
/* Configure TC interrupts for TC TC_CHANNEL_CAPTURE only */
irq_register_handler(TC0_IRQn, 1);
// Init TC to waveform mode.
tc_init(TC0, TC_CHANNEL_TICKCNT,
1 /* Clock = 96MHz / 8 */
| TC_CMR_WAVE // Waveform mode is enabled
| TC_CMR_CPCTRG
);
// Configure waveform frequency and duty cycle.
uint32_t rc = (sysclk_get_peripheral_bus_hz(TC0) /
TC_WAVEFORM_DIVISOR /
TC_WAVEFORM_FREQUENCY);
tc_write_rc(TC0, TC_CHANNEL_TICKCNT, rc);
tc_enable_interrupt(TC0, TC_CHANNEL_TICKCNT, TC_IER_CPCS);
timerEnabled = true;
}
void udd_enable(void)
{
irqflags_t flags;
flags = cpu_irq_save();
#ifdef UHD_ENABLE
//* DUAL ROLE INITIALIZATION
if (otg_dual_enable()) {
// The current mode has been started by otg_dual_enable()
cpu_irq_restore(flags);
return;
}
#else
//* SINGLE DEVICE MODE INITIALIZATION
sysclk_enable_usb();
// Here, only the device mode is possible, then link USBB interrupt to UDD interrupt
irq_register_handler(
#ifdef FREERTOS_USED
(__int_handler)
#endif
udd_interrupt, AVR32_USBB_IRQ, UDD_USB_INT_LEVEL);
// Always authorize asynchronous USB interrupts to exit of sleep mode
pm_asyn_wake_up_enable(AVR32_PM_AWEN_USB_WAKEN_MASK);
#endif
# if (defined USB_ID) && (defined UHD_ENABLE)
// Check that the device mode is selected by ID pin
if (!Is_otg_id_device()) {
cpu_irq_restore(flags);
return; // Device is not the current mode
}
# else
// ID pin not used then force device mode
otg_disable_id_pin();
otg_force_device_mode();
# endif
// Enable USB hardware
otg_enable_pad();
otg_enable();
otg_unfreeze_clock();
(void)Is_otg_clock_frozen();
// Reset internal variables
#if (0!=USB_DEVICE_MAX_EP)
udd_ep_job_table_reset();
#endif
// Set the USB speed requested by configuration file
#ifdef USB_DEVICE_LOW_SPEED
udd_low_speed_enable();
#else
udd_low_speed_disable();
# ifdef USB_DEVICE_HS_SUPPORT
udd_high_speed_enable();
# else
udd_high_speed_disable();
# endif
#endif
otg_ack_vbus_transition();
// Force Vbus interrupt in case of Vbus always with a high level
// This is possible with a short timing between a Host mode stop/start.
if (Is_otg_vbus_high()) {
otg_raise_vbus_transition();
}
otg_enable_vbus_interrupt();
otg_freeze_clock();
#ifndef UDD_NO_SLEEP_MGR
// Initialize the sleep mode authorized for the USB suspend mode
udd_b_idle = false;
sleepmgr_lock_mode(USBB_SLEEP_MODE_USB_SUSPEND);
#endif
cpu_irq_restore(flags);
}
void udd_enable(void)
{
irqflags_t flags;
sysclk_enable_usb();
flags = cpu_irq_save();
//** Enable USB hardware
otg_disable();
(void)Is_otg_enabled();
#ifdef OTG
// Check UID pin state before enter in USB device mode
if (!Is_otg_id_device())
return FALSE;
#else
// Here, only the Device mode is possible, then link USBB interrupt to UDD interrupt
irq_register_handler(udd_interrupt, AVR32_USBB_IRQ, UDD_USB_INT_LEVEL);
otg_force_device_mode();
#endif
otg_disable_pad();
otg_enable_pad();
otg_enable();
otg_unfreeze_clock();
(void)Is_otg_clock_frozen();
#if UC3A3
// For parts with high speed feature, the "USABLE" clock is the UTMI clock,
// and the UTMI clock is disabled in suspend mode. Thereby, the utmi clock
// can't be checked when USB line is not attached or in suspend mode
#else
// Check USB clock
while( !Is_clock_usable() );
#endif
// Reset internal variables
#if (0!=USB_DEVICE_MAX_EP)
udd_ep_job_table_reset();
#endif
// Set the USB speed requested by configuration file
#ifdef USB_DEVICE_LOW_SPEED
udd_low_speed_enable();
#else
udd_low_speed_disable();
# ifdef USB_DEVICE_HS_SUPPORT
udd_high_speed_enable();
# else
udd_high_speed_disable();
# endif
#endif
udd_enable_vbus_interrupt();
otg_freeze_clock();
// Always authorize asynchrone USB interrupts to exit of sleep mode
AVR32_PM.AWEN.usb_waken = 1;
#ifndef UDD_NO_SLEEP_MGR
// Initialize the sleep mode authorized for the USB suspend mode
udd_b_idle = false;
sleepmgr_lock_mode(USBB_SLEEP_MODE_USB_SUSPEND);
#endif
cpu_irq_restore(flags);
}
void usb_task(void *pvParameters)
{
#endif // FREERTOS_USED
// Register the USB interrupt handler to the interrupt controller and enable
// the USB interrupt.
cpu_irq_disable();
irq_register_handler(usb_general_interrupt, AVR32_USBB_IRQ, USB_INT_LEVEL);
cpu_irq_enable();
#ifdef FREERTOS_USED
while (true)
{
// Wait for the semaphore
while (!xSemaphoreTake(usb_tsk_semphr, portMAX_DELAY));
#endif // FREERTOS_USED
// ---- DUAL-ROLE DEVICE/HOST USB MODE -----------------------------------------
#if USB_DEVICE_FEATURE == true && USB_HOST_FEATURE == true
#ifdef FREERTOS_USED
if (usb_device_tsk) vTaskDelete(usb_device_tsk), usb_device_tsk = NULL;
if (usb_host_tsk) vTaskDelete(usb_host_tsk), usb_host_tsk = NULL;
#endif
Usb_input_id_pin();
Usb_enable_id_pin();
if (Is_usb_id_device())
{
g_usb_mode = USB_MODE_DEVICE;
usb_device_task_init();
}
else
{
private_sof_counter = 0;
g_usb_mode = USB_MODE_HOST;
usb_host_task_init();
}
g_old_usb_mode = g_usb_mode; // Store current USB mode, for mode change detection
Usb_raise_id_transition(); // Check no ID transition has been missed during initialization
Usb_enable_id_interrupt();
cpu_irq_enable();
// -----------------------------------------------------------------------------
// ---- DEVICE-ONLY USB MODE ---------------------------------------------------
#elif USB_DEVICE_FEATURE == true
#ifdef FREERTOS_USED
if (usb_device_tsk) vTaskDelete(usb_device_tsk), usb_device_tsk = NULL;
#endif
Usb_force_device_mode();
usb_device_task_init();
// -----------------------------------------------------------------------------
// ---- REDUCED-HOST-ONLY USB MODE ---------------------------------------------
#elif USB_HOST_FEATURE == true
#ifdef FREERTOS_USED
if (usb_host_tsk) vTaskDelete(usb_host_tsk), usb_host_tsk = NULL;
#endif
private_sof_counter = 0;
Usb_force_host_mode();
usb_host_task_init();
// -----------------------------------------------------------------------------
// ---- ERROR, NO MODE ENABLED -------------------------------------------------
#else
#endif
// -----------------------------------------------------------------------------
#ifdef FREERTOS_USED
}
#endif
}
