コード例 #1
0
ファイル: fpga.c プロジェクト: AmkG/iverilog
/*
 * This is the main entry point that ivl uses to invoke me, the code
 * generator.
 */
int target_design(ivl_design_t des)
{
      ivl_scope_t root = ivl_design_root(des);
      const char*path = ivl_design_flag(des, "-o");

      xnf = fopen(path, "w");
      if (xnf == 0) {
	    perror(path);
	    return -1;
      }

      part = ivl_design_flag(des, "part");
      if (part && (part[0] == 0))
	    part = 0;

      arch = ivl_design_flag(des, "arch");
      if (arch && (arch[0] == 0))
	    arch = 0;

      if (arch == 0)
	    arch = "lpm";

      device = device_from_arch(arch);
      if (device == 0) {
	    fprintf(stderr, "Unknown architecture arch=%s\n", arch);
	    return -1;
      }

	/* Call the device driver to generate the netlist header. */
      device->show_header(des);

	/* Catch any behavioral code that is left, and write warnings
	   that it is not supported. */
      ivl_design_process(des, show_process, 0);

	/* Get the pads from the design, and draw them to connect to
	   the associated signals. */
      show_pads(root);

	/* Scan the scopes, looking for gates to draw into the output
	   netlist. */
      show_scope_gates(root, 0);

      show_constants(des);

	/* Call the device driver to close out the file. */
      device->show_footer(des);

      fclose(xnf);
      xnf = 0;
      return 0;
}
コード例 #2
0
ファイル: verilog.c プロジェクト: 13572293130/iverilog
int target_design(ivl_design_t des)
{
      const char*path = ivl_design_flag(des, "-o");
      if (path == 0) {
	    return -1;
      }

      out = fopen(path, "w");
      if (out == 0) {
	    perror(path);
	    return -2;
      }

      fprintf(out, "module %s;\n", ivl_scope_name(ivl_design_root(des)));

	/* Declare all the signals. */
      draw_scoped_objects(des);

	/* Declare logic gates. */
      draw_scope_logic(ivl_design_root(des), 0);

	/* Write out processes. */
      ivl_design_process(des, show_process, 0);

      fprintf(out, "endmodule\n");
      fclose(out);

      return 0;
}
コード例 #3
0
ファイル: fnf.c プロジェクト: BackupTheBerlios/confluence-svn
/* Ivl entry point. */
int target_design(ivl_design_t des)
{
  design = des;
  output = fopen(ivl_design_flag(design, "-o"), "w");
  if (output == 0) {
    /*
    perror("** ERROR: Can not opening output file \"%s\".\n\n", ivl_design_flag(design, "-o"));
    */
    perror(ivl_design_flag(design, "-o"));
    return -1;
  }

  level = 0;
  build_hierarchy(ivl_design_root(design), 0);
  design = 0;
  fclose(output);
  output = 0;
  return 0;
}
コード例 #4
0
ファイル: stub.c プロジェクト: nickg/iverilog
int target_design(ivl_design_t des)
{
      ivl_scope_t*root_scopes;
      unsigned nroot = 0;
      unsigned idx;

      const char*path = ivl_design_flag(des, "-o");
      if (path == 0) {
	    return -1;
      }

      out = fopen(path, "w");
      if (out == 0) {
	    perror(path);
	    return -2;
      }

      for (idx = 0 ; idx < ivl_design_disciplines(des) ; idx += 1) {
	    ivl_discipline_t dis = ivl_design_discipline(des,idx);
	    fprintf(out, "discipline %s\n", ivl_discipline_name(dis));
      }

      ivl_design_roots(des, &root_scopes, &nroot);
      for (idx = 0 ;  idx < nroot ;  idx += 1) {

	    fprintf(out, "root module = %s;\n",
		    ivl_scope_name(root_scopes[idx]));
	    show_scope(root_scopes[idx], 0);
      }

      while (udp_define_list) {
	    struct udp_define_cell*cur = udp_define_list;
	    udp_define_list = cur->next;
	    show_primitive(cur->udp, cur->ref);
	    free(cur);
      }

      ivl_design_process(des, show_process, 0);
      fclose(out);

      return stub_errors;
}
コード例 #5
0
ファイル: d-virtex.c プロジェクト: AmkG/iverilog
/*
 * The show_header function is called before any of the devices of the
 * netlist are scanned.
 *
 * In this function, we look at the ports of the root module to decide
 * if they are to be made into ports. Modules that have PAD attributes
 * are *not* to be used as ports, they will be connected to special
 * PAD devices instead.
 */
static void virtex_show_header(ivl_design_t des)
{
      const char*part_str = 0;

      xilinx_common_header(des);

      xlib = edif_xlibrary_create(edf, "VIRTEX");
      edif_xlibrary_set_celltable(xlib, virtex_celltable);


      if ( (part_str = ivl_design_flag(des, "part")) && (part_str[0] != 0) ) {
	    edif_pstring(edf, "PART", part_str);
      }

      cell_0 = edif_xcell_create(xlib, "GND", 1);
      edif_cell_portconfig(cell_0, 0, "GROUND", IVL_SIP_OUTPUT);

      cell_1 = edif_xcell_create(xlib, "VCC", 1);
      edif_cell_portconfig(cell_1, 0, "VCC", IVL_SIP_OUTPUT);

}
コード例 #6
0
ファイル: imain.c プロジェクト: jeras/iverilog
/*
 * This is the main entry point that Icarus Verilog calls to generate
 * code for a pal.
 */
int target_design(ivl_design_t des)
{
      unsigned idx;
      const char*part;
      ivl_scope_t root;

	/* Get the part type from the design, using the "part"
	   key. Given the part type, try to open the pal description
	   so that we can figure out the device. */
      part = ivl_design_flag(des, "part");
      if ((part == 0) || (*part == 0)) {
	    fprintf(stderr, "error: part must be specified. Specify a\n");
	    fprintf(stderr, "     : type with the -fpart=<type> option.\n");
	    return -1;
      }

      pal = pal_alloc(part);
      if (pal == 0) {
	    fprintf(stderr, "error: %s is not a valid part type.\n", part);
	    return -1;
      }

      assert(pal);

      pins = pal_pins(pal);
      assert(pins > 0);

	/* Allocate the pin array, ready to start assigning resources. */
      bind_pin = calloc(pins, sizeof (struct pal_bind_s));

	/* Connect all the macrocells that drive pins to the pin that
	   they drive. This doesn't yet look at the design, but is
	   initializing the bind_pin array with part information. */
      for (idx = 0 ;  idx < pal_sops(pal) ;  idx += 1) {
	    pal_sop_t sop = pal_sop(pal, idx);
	    int spin = pal_sop_pin(sop);

	    if (spin == 0)
		  continue;

	    assert(spin > 0);
	    bind_pin[spin-1].sop = sop;
      }


	/* Get pin assignments from the user. This is the first and
	   most constrained step. Everything else must work around the
	   results of these bindings. */
      root = ivl_design_root(des);
      get_pad_bindings(root, 0);

      if (pal_errors) {
	    fprintf(stderr, "PAD assignment failed.\n");
	    pal_free(pal);
	    return -1;
      }

	/* Run through the assigned output pins and absorb the output
	   enables that are connected to them. */
      absorb_pad_enables();

	/* Scan all the registers, and assign them to
	   macro-cells. */
      root = ivl_design_root(des);
      fit_registers(root, 0);
      if (pal_errors) {
	    fprintf(stderr, "Register fitting failed.\n");
	    pal_free(pal);
	    return -1;
      }

      fit_logic();
      if (pal_errors) {
	    fprintf(stderr, "Logic fitting failed.\n");
	    pal_free(pal);
	    return -1;
      }

      dump_final_design(stdout);
      emit_jedec(ivl_design_flag(des, "-o"));

      pal_free(pal);
      return 0;
}
コード例 #7
0
ファイル: vlog95.c プロジェクト: 13572293130/iverilog
int target_design(ivl_design_t des)
{
      ivl_scope_t *roots;
      unsigned nroots, idx;
      unsigned has_root_scope = 0;
      const char*path = ivl_design_flag(des, "-o");
	/* Set the indent spacing with the -pspacing flag passed to iverilog
	 * (e.g. -pspacing=4). The default is 2 spaces. */
      const char*spacing_str = ivl_design_flag(des, "spacing");
	/* Use -pfileline to determine if file and line information is
	 * printed for most lines. (e.g. -pfileline=1). The default is no
	 * file/line information will be printed for individual lines. */
      const char*fileline_str = ivl_design_flag(des, "fileline");
	/* Use -pallowsigned to allow signed registers/nets and the
	 * $signed() and $unsigned() system tasks as an extension. */
      const char*allowsigned_str = ivl_design_flag(des, "allowsigned");
      assert(path);

	/* Check for and use a provided indent spacing. */
      if (strcmp(spacing_str, "") != 0) {
	    char *eptr;
	    long value = strtol(spacing_str, &eptr, 0);
	      /* Nothing usable in the spacing string. */
	    if (spacing_str == eptr) {
		  fprintf(stderr, "vlog95 error: Unable to extract spacing "
		                  "increment from string: %s\n", spacing_str);
		  return 1;
	    }
	      /* Extra stuff at the end. */
	    if (*eptr != 0) {
		  fprintf(stderr, "vlog95 error: Extra characters '%s' "
		                  "included at end of spacing string: %s\n",
		                  eptr, spacing_str);
		  return 1;
	    }
	      /* The increment must be greater than zero. */
	    if (value < 1) {
		  fprintf(stderr, "vlog95 error: Spacing increment (%ld) must "
		                  "be greater than zero.\n", value);
		  return 1;
	    }
	      /* An increment of more than sixteen is too much. */
	    if (value > 16) {
		  fprintf(stderr, "vlog95 error: Spacing increment (%ld) must "
		                  "be sixteen or less.\n", value);
		  return 1;
	    }
	    indent_incr = value;
      }

	/* Check to see if file/line information should be printed. */
      if (strcmp(fileline_str, "") != 0) {
	    char *eptr;
	    long value = strtol(fileline_str, &eptr, 0);
	      /* Nothing usable in the file/line string. */
	    if (fileline_str == eptr) {
		  fprintf(stderr, "vlog95 error: Unable to extract file/line "
		                  "information from string: %s\n",
		                  fileline_str);
		  return 1;
	    }
	      /* Extra stuff at the end. */
	    if (*eptr != 0) {
		  fprintf(stderr, "vlog95 error: Extra characters '%s' "
		                  "included at end of file/line string: %s\n",
		                  eptr, fileline_str);
		  return 1;
	    }
	      /* The file/line flag must be positive. */
	    if (value < 0) {
		  fprintf(stderr, "vlog95 error: File/line flag (%ld) must "
		                  "be positive.\n", value);
		  return 1;
	    }
	    emit_file_line = value > 0;
      }

	/* Check to see if we should also print signed constructs. */
      if (strcmp(allowsigned_str, "") != 0) {
	    char *eptr;
	    long value = strtol(allowsigned_str, &eptr, 0);
	      /* Nothing usable in the allow signed string. */
	    if (allowsigned_str == eptr) {
		  fprintf(stderr, "vlog95 error: Unable to extract allow "
		                  "signed information from string: %s\n",
		                  allowsigned_str);
		  return 1;
	    }
	      /* Extra stuff at the end. */
	    if (*eptr != 0) {
		  fprintf(stderr, "vlog95 error: Extra characters '%s' "
		                  "included at end of allow signed string: "
		                  "%s\n", eptr, allowsigned_str);
		  return 1;
	    }
	      /* The allow signed flag must be positive. */
	    if (value < 0) {
		  fprintf(stderr, "vlog95 error: Allow signed flag (%ld) must "
		                  "be positive.\n", value);
		  return 1;
	    }
	    allow_signed = value > 0;
      }

      design = des;

#ifdef HAVE_FOPEN64
      vlog_out = fopen64(path, "w");
#else
      vlog_out = fopen(path, "w");
#endif
      if (vlog_out == 0) {
	    perror(path);
	    return -1;
      }

      fprintf(vlog_out, "/*\n");
      fprintf(vlog_out, " * 1364-1995 Verilog generated by Icarus Verilog "
                        "VLOG95 Code Generator,\n");
      fprintf(vlog_out, " * Version: " VERSION " (" VERSION_TAG ")\n");
      fprintf(vlog_out, " * Converted using %s delays and %s signed support.\n",
                        ivl_design_delay_sel(des),
                        allow_signed ? "with" : "without");
      fprintf(vlog_out, " */\n");

      sim_precision = ivl_design_time_precision(des);

	/* Get all the root modules and then convert each one. */
      ivl_design_roots(des, &roots, &nroots);
	/* Emit any root scope tasks or functions first. */
      for (idx = 0; idx < nroots; idx += 1) {
	    switch(ivl_scope_type(roots[idx])) {
		  case IVL_SCT_FUNCTION:
		  case IVL_SCT_TASK:
			if (! has_root_scope) {
			      fprintf(vlog_out, "module ivl_root_scope;\n");
			      indent += indent_incr;
			      has_root_scope = 1;
			}
			  /* Say this task/function has a parent so the
			   * definition is emitted correctly. */
			emit_scope(roots[idx], roots[idx]);
			break;
		  default:
			break;
	    }
      }
      if (has_root_scope) {
	    indent -= indent_incr;
	    assert(indent == 0);
	    fprintf(vlog_out, "endmodule /* ivl_root_scope */\n");
      }
	/* Emit the rest of the scope objects. */
      for (idx = 0; idx < nroots; idx += 1) emit_scope(roots[idx], 0);

      free_emitted_scope_list();

	/* Emit any UDP definitions that the design used. */
      emit_udp_list();

	/* Emit any UDPs that are Icarus generated (D-FF). */
      emit_icarus_generated_udps();

	/* If there were errors then add this information to the output. */
      if (vlog_errors) {
	    fprintf(vlog_out, "\n");
	    fprintf(vlog_out, "/*\n");
	    if (vlog_errors == 1) {
		  fprintf(vlog_out, " * There was 1 error during "
		                    "translation.\n");
	    } else {
		  fprintf(vlog_out, " * There were %d errors during "
		                    "translation.\n",
		                    vlog_errors);
	    }
	    fprintf(vlog_out, " */\n");
	      /* Add something that makes the file invalid to make sure
	       * the user knows there were errors. */
	    fprintf(vlog_out, "<Add some text to make sure this file is not "
	                      "valid Verilog>\n");
      }

      fclose(vlog_out);

	/* A do nothing call to prevent warnings about this routine not
	 * being used. */
      dump_nexus_information(0, 0);

      return vlog_errors;
}