static void edif_show_footer(ivl_design_t des)
{
unsigned nref = 0;
struct nexus_recall*cur;
ivl_scope_t root = ivl_design_root(des);
edif_show_consts(des);
for (cur = net_list ; cur ; cur = cur->next) {
fprintf(xnf, "(net (rename N%u \"%s\") (joined %s))\n",
nref, ivl_nexus_name(cur->nex), cur->joined);
nref += 1;
}
fprintf(xnf, " )\n"); /* end the (contents ) sexp */
fprintf(xnf, " )\n"); /* end the (view ) sexp */
fprintf(xnf, " )\n"); /* end the (cell ) sexp */
fprintf(xnf, " )\n"); /* end the (library ) sexp */
/* Make an instance of the defined object */
fprintf(xnf, " (design %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellRef %s (libraryRef DESIGN))\n",
ivl_scope_name(root));
if (part)
fprintf(xnf, " (property PART (string \"%s\"))\n", part);
fprintf(xnf, " )\n");
fprintf(xnf, ")\n"); /* end the (edif ) sexp */
}
int target_design(ivl_design_t des)
{
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
return -1;
}
out = fopen(path, "w");
if (out == 0) {
perror(path);
return -2;
}
fprintf(out, "module %s;\n", ivl_scope_name(ivl_design_root(des)));
/* Declare all the signals. */
draw_scoped_objects(des);
/* Declare logic gates. */
draw_scope_logic(ivl_design_root(des), 0);
/* Write out processes. */
ivl_design_process(des, show_process, 0);
fprintf(out, "endmodule\n");
fclose(out);
return 0;
}
static void show_lpm_ufunc(ivl_lpm_t net)
{
unsigned width = ivl_lpm_width(net);
unsigned ports = ivl_lpm_size(net);
ivl_scope_t def = ivl_lpm_define(net);
ivl_nexus_t nex;
unsigned idx;
fprintf(out, " LPM_UFUNC %s: <call=%s, width=%u, ports=%u>\n",
ivl_lpm_basename(net), ivl_scope_name(def), width, ports);
show_lpm_delays(net);
nex = ivl_lpm_q(net);
if (width != width_of_nexus(nex)) {
fprintf(out, " ERROR: Q output nexus width=%u "
" does not match part width\n", width_of_nexus(nex));
stub_errors += 1;
}
fprintf(out, " Q: %p\n", nex);
for (idx = 0 ; idx < ports ; idx += 1) {
nex = ivl_lpm_data(net, idx);
fprintf(out, " D%u: %p <width=%u>\n", idx,
nex, width_of_nexus(nex));
}
}
void draw_ufunc_real(ivl_expr_t expr)
{
ivl_scope_t def = ivl_expr_def(expr);
ivl_signal_t retval = ivl_scope_port(def, 0);
unsigned idx;
/* If this is an automatic function, allocate the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%alloc S_%p;\n", def);
}
assert(ivl_expr_parms(expr) == (ivl_scope_ports(def)-1));
for (idx = 0 ; idx < ivl_expr_parms(expr) ; idx += 1) {
ivl_signal_t port = ivl_scope_port(def, idx+1);
draw_function_argument(port, ivl_expr_parm(expr, idx));
}
/* Call the function */
fprintf(vvp_out, " %%fork TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
fprintf(vvp_out, " %%join;\n");
/* Return value signal cannot be an array. */
assert(ivl_signal_dimensions(retval) == 0);
/* Load the result into a word. */
fprintf(vvp_out, " %%load/real v%p_0;\n", retval);
/* If this is an automatic function, free the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%free S_%p;\n", def);
}
}
static void draw_ufunc_preamble(ivl_expr_t expr)
{
ivl_scope_t def = ivl_expr_def(expr);
unsigned idx;
/* If this is an automatic function, allocate the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%alloc S_%p;\n", def);
}
/* evaluate the expressions and send the results to the
function ports. */
assert(ivl_expr_parms(expr) == (ivl_scope_ports(def)-1));
for (idx = 0 ; idx < ivl_expr_parms(expr) ; idx += 1) {
ivl_signal_t port = ivl_scope_port(def, idx+1);
draw_function_argument(port, ivl_expr_parm(expr, idx));
}
/* Call the function */
fprintf(vvp_out, " %%fork TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
fprintf(vvp_out, " %%join;\n");
}
static void draw_ufunc_preamble(ivl_expr_t expr)
{
ivl_scope_t def = ivl_expr_def(expr);
unsigned idx;
/* If this is an automatic function, allocate the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%alloc S_%p;\n", def);
}
/* Evaluate the expressions and send the results to the
function ports. Do this in two passes - evaluate,
then send - this avoids the function input variables
being overwritten if the same (non-automatic) function
is called in one of the exressions. */
assert(ivl_expr_parms(expr) == (ivl_scope_ports(def)-1));
for (idx = 0 ; idx < ivl_expr_parms(expr) ; idx += 1) {
ivl_signal_t port = ivl_scope_port(def, idx+1);
draw_eval_function_argument(port, ivl_expr_parm(expr, idx));
}
for (idx = ivl_expr_parms(expr) ; idx > 0 ; idx -= 1) {
ivl_signal_t port = ivl_scope_port(def, idx);
draw_send_function_argument(port);
}
/* Call the function */
fprintf(vvp_out, " %%fork TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
fprintf(vvp_out, " %%join;\n");
}
static void display_multi_driver_error(ivl_nexus_t nex, unsigned ndrivers,
mdriver_type_t type)
{
unsigned idx;
unsigned scope_len = UINT_MAX;
ivl_signal_t sig = 0;
/* Find the signal. */
for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) {
ivl_nexus_ptr_t ptr = ivl_nexus_ptr(nex, idx);
ivl_signal_t tsig = ivl_nexus_ptr_sig(ptr);
if (tsig != 0) {
ivl_scope_t scope;
unsigned len;
if (ivl_signal_local(tsig)) continue;
/* If this is not a local signal then find the signal
* that has the shortest scope (is the furthest up
* the hierarchy). */
scope = ivl_signal_scope(tsig);
assert(scope);
len = strlen(ivl_scope_name(scope));
if (len < scope_len) {
scope_len = len;
sig = tsig;
}
}
}
assert(sig);
fprintf(stderr, "%s:%u: vvp.tgt error: ",
ivl_signal_file(sig), ivl_signal_lineno(sig));
switch (type) {
case MDRV_UWIRE:
if (ivl_signal_type(sig) != IVL_SIT_UWIRE) {
fprintf(stderr, "(implicit) ");
}
fprintf(stderr, "uwire");
break;
case MDRV_REAL:
assert(ivl_signal_type(sig) == IVL_SIT_TRI);
if (ivl_signal_data_type(sig) != IVL_VT_REAL) {
fprintf(stderr, "(implicit) ");
}
fprintf(stderr, "wire real");
break;
default:
assert(0);;
}
fprintf(stderr, " \"%s\" must have a single driver, found (%u).\n",
ivl_signal_basename(sig), ndrivers);
vvp_errors += 1;
}
static int show_stmt_utask(ivl_statement_t net)
{
ivl_scope_t task = ivl_stmt_call(net);
fprintf(vvp_out, " %%fork TD_%s",
vvp_mangle_id(ivl_scope_name(task)));
fprintf(vvp_out, ", S_%p;\n", task);
fprintf(vvp_out, " %%join;\n");
clear_expression_lookaside();
return 0;
}
static void draw_ufunc_preamble(ivl_expr_t expr)
{
ivl_scope_t def = ivl_expr_def(expr);
unsigned idx;
/* If this is an automatic function, allocate the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%alloc S_%p;\n", def);
}
/* Evaluate the expressions and send the results to the
function ports. Do this in two passes - evaluate,
then send - this avoids the function input variables
being overwritten if the same (non-automatic) function
is called in one of the expressions. */
assert(ivl_expr_parms(expr) == (ivl_scope_ports(def)-1));
for (idx = 0 ; idx < ivl_expr_parms(expr) ; idx += 1) {
ivl_signal_t port = ivl_scope_port(def, idx+1);
draw_eval_function_argument(port, ivl_expr_parm(expr, idx));
}
for (idx = ivl_expr_parms(expr) ; idx > 0 ; idx -= 1) {
ivl_signal_t port = ivl_scope_port(def, idx);
draw_send_function_argument(port);
}
/* Call the function */
switch (ivl_expr_value(expr)) {
case IVL_VT_VOID:
fprintf(vvp_out, " %%callf/void TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
break;
case IVL_VT_REAL:
fprintf(vvp_out, " %%callf/real TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
break;
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
fprintf(vvp_out, " %%callf/vec4 TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
break;
case IVL_VT_STRING:
fprintf(vvp_out, " %%callf/str TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
break;
case IVL_VT_CLASS:
case IVL_VT_DARRAY:
case IVL_VT_QUEUE:
fprintf(vvp_out, " %%callf/obj TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
break;
default:
fprintf(vvp_out, " %%fork TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
fprintf(vvp_out, " %%join;\n");
break;
}
}
static void show_function_call(ivl_expr_t net, unsigned ind)
{
ivl_scope_t def = ivl_expr_def(net);
const char*sign = ivl_expr_signed(net)? "signed" : "unsigned";
const char*vt = vt_type_string(net);
unsigned idx;
fprintf(out, "%*s<%s %s function %s with %u arguments (width=%u)>\n",
ind, "", vt, sign, ivl_scope_name(def), ivl_expr_parms(net),
ivl_expr_width(net));
for (idx = 0 ; idx < ivl_expr_parms(net) ; idx += 1)
show_expression(ivl_expr_parm(net,idx), ind+4);
}
static void edif_show_header_generic(ivl_design_t des, const char*library)
{
ivl_scope_t root = ivl_design_root(des);
/* write the primitive header */
fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
fprintf(xnf, " (edifVersion 2 0 0)\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
fprintf(xnf, " (status\n");
fprintf(xnf, " (written\n");
fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
fprintf(xnf, " (author \"unknown\")\n");
fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
/* Write out the external references here? */
fputs(library, xnf);
/* Write out the library header */
fprintf(xnf, " (library DESIGN\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (technology (numberDefinition))\n");
/* The root module is a cell in the library. */
fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellType GENERIC)\n");
fprintf(xnf, " (view net\n");
fprintf(xnf, " (viewType NETLIST)\n");
fprintf(xnf, " (interface\n");
show_root_ports_edif(root);
fprintf(xnf, " )\n"); /* end the (interface ) sexp */
fprintf(xnf, " (contents\n");
}
static void draw_lpm_ufunc(ivl_lpm_t net)
{
unsigned idx;
ivl_scope_t def = ivl_lpm_define(net);
const char*dly = draw_lpm_output_delay(net);
fprintf(vvp_out, "L_%p%s .ufunc TD_%s, %u", net, dly,
vvp_mangle_id(ivl_scope_name(def)),
ivl_lpm_width(net));
/* Print all the net signals that connect to the input of the
function. */
for (idx = 0 ; idx < ivl_lpm_size(net) ; idx += 1) {
fprintf(vvp_out, ", %s", draw_net_input(ivl_lpm_data(net, idx)));
}
assert((ivl_lpm_size(net)+1) == ivl_scope_ports(def));
/* Now print all the variables in the function scope that
receive the input values given in the previous list. */
for (idx = 0 ; idx < ivl_lpm_size(net) ; idx += 1) {
ivl_signal_t psig = ivl_scope_port(def, idx+1);
if (idx == 0)
fprintf(vvp_out, " (");
else
fprintf(vvp_out, ", ");
assert(ivl_signal_dimensions(psig) == 0);
fprintf(vvp_out, "v%p_0", psig);
}
fprintf(vvp_out, ")");
/* Now print the reference to the signal from which the
result is collected. */
{ ivl_signal_t psig = ivl_scope_port(def, 0);
assert(ivl_lpm_width(net) == ivl_signal_width(psig));
assert(ivl_signal_dimensions(psig) == 0);
fprintf(vvp_out, " v%p_0", psig);
}
/* Finally, print the scope identifier. */
fprintf(vvp_out, " S_%p;\n", def);
}
int draw_func_definition(ivl_scope_t scope)
{
int rc = 0;
ivl_statement_t def = ivl_scope_def(scope);
fprintf(vvp_out, "TD_%s ;\n", vvp_mangle_id(ivl_scope_name(scope)));
clear_expression_lookaside();
assert(def);
rc += show_statement(def, scope);
fprintf(vvp_out, " %%end;\n");
thread_count += 1;
return rc;
}
int target_design(ivl_design_t des)
{
ivl_scope_t*root_scopes;
unsigned nroot = 0;
unsigned idx;
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
return -1;
}
out = fopen(path, "w");
if (out == 0) {
perror(path);
return -2;
}
for (idx = 0 ; idx < ivl_design_disciplines(des) ; idx += 1) {
ivl_discipline_t dis = ivl_design_discipline(des,idx);
fprintf(out, "discipline %s\n", ivl_discipline_name(dis));
}
ivl_design_roots(des, &root_scopes, &nroot);
for (idx = 0 ; idx < nroot ; idx += 1) {
fprintf(out, "root module = %s;\n",
ivl_scope_name(root_scopes[idx]));
show_scope(root_scopes[idx], 0);
}
while (udp_define_list) {
struct udp_define_cell*cur = udp_define_list;
udp_define_list = cur->next;
show_primitive(cur->udp, cur->ref);
free(cur);
}
ivl_design_process(des, show_process, 0);
fclose(out);
return stub_errors;
}
static void show_nexus_details(ivl_signal_t net, ivl_nexus_t nex)
{
unsigned idx;
for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) {
ivl_net_const_t con;
ivl_net_logic_t logic;
ivl_lpm_t lpm;
ivl_signal_t sig;
ivl_switch_t swt;
ivl_branch_t bra;
ivl_nexus_ptr_t ptr = ivl_nexus_ptr(nex, idx);
const char*dr0 = str_tab[ivl_nexus_ptr_drive0(ptr)];
const char*dr1 = str_tab[ivl_nexus_ptr_drive1(ptr)];
if ((sig = ivl_nexus_ptr_sig(ptr))) {
fprintf(out, " SIG %s word=%u (%s0, %s1)",
ivl_signal_name(sig), ivl_nexus_ptr_pin(ptr), dr0, dr1);
if (ivl_signal_width(sig) != ivl_signal_width(net)) {
fprintf(out, " (ERROR: Width=%u)",
ivl_signal_width(sig));
stub_errors += 1;
}
if (ivl_signal_data_type(sig) != ivl_signal_data_type(net)) {
fprintf(out, " (ERROR: data type mismatch)");
stub_errors += 1;
}
fprintf(out, "\n");
} else if ((logic = ivl_nexus_ptr_log(ptr))) {
fprintf(out, " LOG %s.%s[%u] (%s0, %s1)\n",
ivl_scope_name(ivl_logic_scope(logic)),
ivl_logic_basename(logic),
ivl_nexus_ptr_pin(ptr), dr0, dr1);
} else if ((lpm = ivl_nexus_ptr_lpm(ptr))) {
fprintf(out, " LPM %s.%s (%s0, %s1)\n",
ivl_scope_name(ivl_lpm_scope(lpm)),
ivl_lpm_basename(lpm), dr0, dr1);
} else if ((swt = ivl_nexus_ptr_switch(ptr))) {
fprintf(out, " SWITCH %s.%s\n",
ivl_scope_name(ivl_switch_scope(swt)),
ivl_switch_basename(swt));
} else if ((con = ivl_nexus_ptr_con(ptr))) {
signal_nexus_const(net, ptr, con);
} else if ((bra = ivl_nexus_ptr_branch(ptr))) {
fprintf(out, " BRANCH %p terminal %u\n",
bra, ivl_nexus_ptr_pin(ptr));
} else {
fprintf(out, " ?[%u] (%s0, %s1)\n",
ivl_nexus_ptr_pin(ptr), dr0, dr1);
}
}
}
static int show_scope(ivl_scope_t net, void*x)
{
unsigned idx;
const char *is_auto;
fprintf(out, "scope: %s (%u parameters, %u signals, %u logic)",
ivl_scope_name(net), ivl_scope_params(net),
ivl_scope_sigs(net), ivl_scope_logs(net));
is_auto = ivl_scope_is_auto(net) ? "automatic " : "";
switch (ivl_scope_type(net)) {
case IVL_SCT_MODULE:
fprintf(out, " module %s%s", ivl_scope_tname(net),
ivl_scope_is_cell(net) ? " (cell)" : "");
break;
case IVL_SCT_FUNCTION:
fprintf(out, " function %s%s", is_auto, ivl_scope_tname(net));
break;
case IVL_SCT_BEGIN:
fprintf(out, " begin : %s", ivl_scope_tname(net));
break;
case IVL_SCT_FORK:
fprintf(out, " fork : %s", ivl_scope_tname(net));
break;
case IVL_SCT_TASK:
fprintf(out, " task %s%s", is_auto, ivl_scope_tname(net));
break;
default:
fprintf(out, " type(%u) %s", ivl_scope_type(net),
ivl_scope_tname(net));
break;
}
fprintf(out, " time units = 1e%d\n", ivl_scope_time_units(net));
fprintf(out, " time precision = 1e%d\n", ivl_scope_time_precision(net));
for (idx = 0 ; idx < ivl_scope_attr_cnt(net) ; idx += 1) {
ivl_attribute_t attr = ivl_scope_attr_val(net, idx);
switch (attr->type) {
case IVL_ATT_VOID:
fprintf(out, " (* %s *)\n", attr->key);
break;
case IVL_ATT_STR:
fprintf(out, " (* %s = \"%s\" *)\n", attr->key,
attr->val.str);
break;
case IVL_ATT_NUM:
fprintf(out, " (* %s = %ld *)\n", attr->key,
attr->val.num);
break;
}
}
for (idx = 0 ; idx < ivl_scope_params(net) ; idx += 1)
show_parameter(ivl_scope_param(net, idx));
for (idx = 0 ; idx < ivl_scope_enumerates(net) ; idx += 1)
show_enumerate(ivl_scope_enumerate(net, idx));
for (idx = 0 ; idx < ivl_scope_sigs(net) ; idx += 1)
show_signal(ivl_scope_sig(net, idx));
for (idx = 0 ; idx < ivl_scope_events(net) ; idx += 1)
show_event(ivl_scope_event(net, idx));
for (idx = 0 ; idx < ivl_scope_logs(net) ; idx += 1)
show_logic(ivl_scope_log(net, idx));
for (idx = 0 ; idx < ivl_scope_lpms(net) ; idx += 1)
show_lpm(ivl_scope_lpm(net, idx));
for (idx = 0 ; idx < ivl_scope_switches(net) ; idx += 1)
show_switch(ivl_scope_switch(net, idx));
switch (ivl_scope_type(net)) {
case IVL_SCT_FUNCTION:
case IVL_SCT_TASK:
fprintf(out, " scope function/task definition\n");
if (ivl_scope_def(net) == 0) {
fprintf(out, " ERROR: scope missing required task definition\n");
stub_errors += 1;
} else {
show_statement(ivl_scope_def(net), 6);
}
break;
default:
if (ivl_scope_def(net)) {
fprintf(out, " ERROR: scope has an attached task definition:\n");
show_statement(ivl_scope_def(net), 6);
stub_errors += 1;
}
break;
}
fprintf(out, "end scope %s\n", ivl_scope_name(net));
return ivl_scope_children(net, show_scope, 0);
}
struct vector_info draw_ufunc_expr(ivl_expr_t expr, unsigned wid)
{
unsigned idx;
unsigned swid = ivl_expr_width(expr);
ivl_scope_t def = ivl_expr_def(expr);
ivl_signal_t retval = ivl_scope_port(def, 0);
struct vector_info res;
unsigned load_wid;
/* If this is an automatic function, allocate the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%alloc S_%p;\n", def);
}
/* evaluate the expressions and send the results to the
function ports. */
assert(ivl_expr_parms(expr) == (ivl_scope_ports(def)-1));
for (idx = 0 ; idx < ivl_expr_parms(expr) ; idx += 1) {
ivl_signal_t port = ivl_scope_port(def, idx+1);
draw_function_argument(port, ivl_expr_parm(expr, idx));
}
/* Call the function */
fprintf(vvp_out, " %%fork TD_%s", vvp_mangle_id(ivl_scope_name(def)));
fprintf(vvp_out, ", S_%p;\n", def);
fprintf(vvp_out, " %%join;\n");
/* Fresh basic block starts after the join. */
clear_expression_lookaside();
/* The return value is in a signal that has the name of the
expression. Load that into the thread and return the
vector result. */
res.base = allocate_vector(wid);
res.wid = wid;
if (res.base == 0) {
fprintf(stderr, "%s:%u: vvp.tgt error: "
"Unable to allocate %u thread bits for function result.\n",
ivl_expr_file(expr), ivl_expr_lineno(expr), wid);
vvp_errors += 1;
return res;
}
assert(res.base != 0);
load_wid = swid;
if (load_wid > ivl_signal_width(retval))
load_wid = ivl_signal_width(retval);
assert(ivl_signal_dimensions(retval) == 0);
fprintf(vvp_out, " %%load/v %u, v%p_0, %u;\n",
res.base, retval, load_wid);
/* Pad the signal value with zeros. */
if (load_wid < wid)
pad_expr_in_place(expr, res, swid);
/* If this is an automatic function, free the local storage. */
if (ivl_scope_is_auto(def)) {
fprintf(vvp_out, " %%free S_%p;\n", def);
}
return res;
}
static void show_signal(ivl_signal_t net)
{
unsigned idx;
const char*type = "?";
const char*port = "";
const char*data_type = "?";
const char*sign = ivl_signal_signed(net)? "signed" : "unsigned";
switch (ivl_signal_type(net)) {
case IVL_SIT_REG:
type = "reg";
break;
case IVL_SIT_TRI:
type = "tri";
break;
case IVL_SIT_TRI0:
type = "tri0";
break;
case IVL_SIT_TRI1:
type = "tri1";
break;
case IVL_SIT_UWIRE:
type = "uwire";
break;
default:
break;
}
switch (ivl_signal_port(net)) {
case IVL_SIP_INPUT:
port = "input ";
break;
case IVL_SIP_OUTPUT:
port = "output ";
break;
case IVL_SIP_INOUT:
port = "inout ";
break;
case IVL_SIP_NONE:
break;
}
switch (ivl_signal_data_type(net)) {
case IVL_VT_BOOL:
data_type = "bool";
break;
case IVL_VT_LOGIC:
data_type = "logic";
break;
case IVL_VT_REAL:
data_type = "real";
break;
default:
data_type = "?data?";
break;
}
const char*discipline_txt = "NONE";
if (ivl_signal_discipline(net)) {
ivl_discipline_t dis = ivl_signal_discipline(net);
discipline_txt = ivl_discipline_name(dis);
}
for (idx = 0 ; idx < ivl_signal_array_count(net) ; idx += 1) {
ivl_nexus_t nex = ivl_signal_nex(net, idx);
fprintf(out, " %s %s %s%s[%d:%d] %s[word=%u, adr=%d] "
"<width=%u%s> <discipline=%s> ",
type, sign, port, data_type,
ivl_signal_msb(net), ivl_signal_lsb(net),
ivl_signal_basename(net),
idx, ivl_signal_array_base(net)+idx,
ivl_signal_width(net),
ivl_signal_local(net)? ", local":"",
discipline_txt);
if (nex == NULL) {
fprintf(out, "nexus=<virtual>\n");
continue;
} else {
fprintf(out, "nexus=%p\n", nex);
}
show_nexus_details(net, nex);
}
for (idx = 0 ; idx < ivl_signal_npath(net) ; idx += 1) {
ivl_delaypath_t path = ivl_signal_path(net,idx);
ivl_nexus_t nex = ivl_path_source(path);
ivl_nexus_t con = ivl_path_condit(path);
int posedge = ivl_path_source_posedge(path);
int negedge = ivl_path_source_negedge(path);
fprintf(out, " path %p", nex);
if (posedge) fprintf(out, " posedge");
if (negedge) fprintf(out, " negedge");
if (con) fprintf(out, " (if %p)", con);
else if (ivl_path_is_condit(path)) fprintf(out, " (ifnone)");
fprintf(out, " %" PRIu64 ",%" PRIu64 ",%" PRIu64
" %" PRIu64 ",%" PRIu64 ",%" PRIu64
" %" PRIu64 ",%" PRIu64 ",%" PRIu64
" %" PRIu64 ",%" PRIu64 ",%" PRIu64,
ivl_path_delay(path, IVL_PE_01),
ivl_path_delay(path, IVL_PE_10),
ivl_path_delay(path, IVL_PE_0z),
ivl_path_delay(path, IVL_PE_z1),
ivl_path_delay(path, IVL_PE_1z),
ivl_path_delay(path, IVL_PE_z0),
ivl_path_delay(path, IVL_PE_0x),
ivl_path_delay(path, IVL_PE_x1),
ivl_path_delay(path, IVL_PE_1x),
ivl_path_delay(path, IVL_PE_x0),
ivl_path_delay(path, IVL_PE_xz),
ivl_path_delay(path, IVL_PE_zx));
fprintf(out, " scope=%s\n", ivl_scope_name(ivl_path_scope(path)));
}
for (idx = 0 ; idx < ivl_signal_attr_cnt(net) ; idx += 1) {
ivl_attribute_t atr = ivl_signal_attr_val(net, idx);
switch (atr->type) {
case IVL_ATT_STR:
fprintf(out, " %s = %s\n", atr->key, atr->val.str);
break;
case IVL_ATT_NUM:
fprintf(out, " %s = %ld\n", atr->key, atr->val.num);
break;
case IVL_ATT_VOID:
fprintf(out, " %s\n", atr->key);
break;
}
}
}
static void edif_show_generic_dff(ivl_lpm_t net)
{
ivl_nexus_t nex;
char jbuf[1024];
unsigned idx;
ivl_nexus_t aclr = ivl_lpm_async_clr(net);
ivl_nexus_t aset = ivl_lpm_async_set(net);
ivl_expr_t avalue = 0;
const char*abits = 0;
const char*fdcell = "FDCE";
if (aset != 0) {
fdcell = "FDCPE";
avalue = ivl_lpm_aset_value(net);
assert(avalue);
abits = ivl_expr_bits(avalue);
assert(abits);
}
for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
edif_uref += 1;
fprintf(xnf, "(instance (rename U%u \"%s.%s[%u]\")",
edif_uref, ivl_scope_name(ivl_lpm_scope(net)),
ivl_lpm_basename(net), idx);
fprintf(xnf, " (viewRef net"
" (cellRef %s (libraryRef VIRTEX))))\n",
fdcell);
nex = ivl_lpm_q(net, idx);
sprintf(jbuf, "(portRef Q (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(nex, jbuf);
nex = ivl_lpm_data(net, idx);
sprintf(jbuf, "(portRef D (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(nex, jbuf);
nex = ivl_lpm_clk(net);
sprintf(jbuf, "(portRef C (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(nex, jbuf);
if ((nex = ivl_lpm_enable(net))) {
sprintf(jbuf, "(portRef CE (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(nex, jbuf);
}
if (aclr) {
sprintf(jbuf, "(portRef CLR (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(aclr, jbuf);
}
if (aset) {
if (abits[idx] == '1') {
sprintf(jbuf, "(portRef PRE (instanceRef U%u))",
edif_uref);
edif_set_nexus_joint(aset, jbuf);
} else {
assert(aclr == 0);
sprintf(jbuf, "(portRef CLR (instanceRef U%u))",
edif_uref);
edif_set_nexus_joint(aset, jbuf);
}
}
}
}
static void draw_lpm_in_scope(ivl_lpm_t net)
{
switch (ivl_lpm_type(net)) {
case IVL_LPM_ABS:
draw_lpm_abs(net);
return;
case IVL_LPM_CAST_INT:
draw_lpm_cast_int(net);
return;
case IVL_LPM_CAST_REAL:
draw_lpm_cast_real(net);
return;
case IVL_LPM_ADD:
case IVL_LPM_SUB:
case IVL_LPM_MULT:
case IVL_LPM_DIVIDE:
case IVL_LPM_MOD:
case IVL_LPM_POW:
draw_lpm_add(net);
return;
case IVL_LPM_ARRAY:
draw_lpm_array(net);
return;
case IVL_LPM_PART_VP:
draw_lpm_part(net);
return;
case IVL_LPM_PART_PV:
draw_lpm_part_pv(net);
return;
case IVL_LPM_CONCAT:
draw_lpm_concat(net);
return;
case IVL_LPM_FF:
draw_lpm_ff(net);
return;
case IVL_LPM_CMP_EEQ:
case IVL_LPM_CMP_EQ:
case IVL_LPM_CMP_GE:
case IVL_LPM_CMP_GT:
case IVL_LPM_CMP_NE:
case IVL_LPM_CMP_NEE:
draw_lpm_cmp(net);
return;
case IVL_LPM_MUX:
draw_lpm_mux(net);
return;
case IVL_LPM_RE_AND:
draw_lpm_re(net, "and");
return;
case IVL_LPM_RE_OR:
draw_lpm_re(net, "or");
return;
case IVL_LPM_RE_XOR:
draw_lpm_re(net, "xor");
return;
case IVL_LPM_RE_NAND:
draw_lpm_re(net, "nand");
return;
case IVL_LPM_RE_NOR:
draw_lpm_re(net, "nor");
return;
case IVL_LPM_RE_XNOR:
draw_lpm_re(net, "xnor");
return;
case IVL_LPM_REPEAT:
draw_lpm_repeat(net);
return;
case IVL_LPM_SHIFTL:
case IVL_LPM_SHIFTR:
draw_lpm_shiftl(net);
return;
case IVL_LPM_SIGN_EXT:
draw_lpm_sign_ext(net);
return;
case IVL_LPM_SFUNC:
draw_lpm_sfunc(net);
return;
case IVL_LPM_UFUNC:
draw_lpm_ufunc(net);
return;
default:
fprintf(stderr, "XXXX LPM not supported: %s.%s\n",
ivl_scope_name(ivl_lpm_scope(net)), ivl_lpm_basename(net));
}
}
