s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { switch (hw->mac.type) { case ixgbe_mac_82598EB: ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa); break; case ixgbe_mac_82599EB: case ixgbe_mac_X540: ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa, map); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map); break; default: break; } return 0; }
/** * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure Rx Data Arbiter and credits for each traffic class. */ s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { s32 ret = IXGBE_NOT_IMPLEMENTED; u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); ixgbe_dcb_unpack_max_cee(dcb_config, max); ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); switch (hw->mac.type) { case ixgbe_mac_82598EB: ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); break; case ixgbe_mac_82599EB: case ixgbe_mac_X540: ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid, tsa, map); break; default: break; } return ret; }
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { switch (hw->mac.type) { case ixgbe_mac_82598EB: ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa); break; case ixgbe_mac_82599EB: case ixgbe_mac_X540: case ixgbe_mac_X550: case ixgbe_mac_X550EM_x: #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa, map); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map); break; #endif default: break; } return 0; }
s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { s32 ret = 0; if (hw->mac.type == ixgbe_mac_82598EB) ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); else if (hw->mac.type == ixgbe_mac_82599EB) ret = ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); return ret; }
/** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config); ixgbe_dcb_config_82599(hw); ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); ixgbe_dcb_config_pfc_82599(hw, dcb_config); ixgbe_dcb_config_tc_stats_82599(hw); return 0; }
/** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @refill: refill credits index by traffic class * @max: max credits index by traffic class * @bwg_id: bandwidth grouping indexed by traffic class * @prio_type: priority type indexed by traffic class * @pfc_en: enabled pfc bitmask * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc) { ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type, prio_tc); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, prio_type); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, prio_type, prio_tc); ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); ixgbe_dcb_config_tc_stats_82599(hw); return 0; }
/** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa, map); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map); return 0; }
/** * ixgbe_dcb_hw_config_82599 - Configure and enable DCB * @hw: pointer to hardware structure * @dcb_config: pointer to ixgbe_dcb_config structure * * Configure dcb settings and enable dcb mode. */ s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed, u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa, u8 *map) { UNREFERENCED_1PARAMETER(link_speed); ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa, map); ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa); ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map); return IXGBE_SUCCESS; }