int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) { embeddedice_reg_t *ice_reg = reg->arch_info; u8 reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; u8 field1_out[1]; u8 field2_out[1]; jtag_add_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); fields[0].tap = ice_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, reg_addr); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1); fields[0].in_value = reg->value; jtag_set_check_value(fields+0, check_value, check_mask, NULL); /* when reading the DCC data register, leaving the address field set to * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); jtag_add_dr_scan(3, fields, -1); return ERROR_OK; }
/* just read data (instruction and data-out = don't care) */ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) { scan_field_t fields[3]; jtag_add_end_state(TAP_PD); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[1].device = jtag_info->chain_pos; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[2].device = jtag_info->chain_pos; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1, NULL); jtag_add_runtest(0, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { jtag_execute_queue(); if (in) { DEBUG("in: 0x%8.8x", *in); } else { ERROR("BUG: called with in == NULL"); } } #endif return ERROR_OK; }
/* send <size> words of 32 bit to the DCC * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) { scan_field_t fields[3]; u8 field0_out[4]; u8 field1_out[1]; u8 field2_out[1]; jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = field0_out; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 1); fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; while (size > 0) { buf_set_u32(fields[0].out_value, 0, 32, *data); jtag_add_dr_scan(3, fields, -1); data++; size--; } /* call to jtag_execute_queue() intentionally omitted */ return ERROR_OK; }
void embeddedice_write_reg(reg_t *reg, u32 value) { embeddedice_reg_t *ice_reg = reg->arch_info; LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); jtag_add_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); u8 reg_addr = ice_reg->addr & 0x1f; embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); }
/* wait for DCC control register R/W handshake bit to become active */ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) { scan_field_t fields[3]; u8 field0_in[4]; u8 field1_out[1]; u8 field2_out[1]; int retval; int hsact; struct timeval lap; struct timeval now; if (hsbit == EICE_COMM_CTRL_WBIT) hsact = 1; else if (hsbit == EICE_COMM_CTRL_RBIT) hsact = 0; else return ERROR_INVALID_ARGUMENTS; jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = field0_in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1); gettimeofday(&lap, NULL); do { jtag_add_dr_scan(3, fields, -1); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; if (buf_get_u32(field0_in, hsbit, 1) == hsact) return ERROR_OK; gettimeofday(&now, NULL); } while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout); return ERROR_TARGET_TIMEOUT; }
/* receive <size> words of 32 bit from the DCC * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) { scan_field_t fields[3]; u8 field1_out[1]; u8 field2_out[1]; jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1); while (size > 0) { /* when reading the last item, set the register address to the DCC control reg, * to avoid reading additional data from the DCC data reg */ if (size == 1) buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = data; jtag_add_dr_scan(3, fields, -1); data++; size--; } return jtag_execute_queue(); }
/* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be==1) or little (be==0) endianness */ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) { scan_field_t fields[3]; jtag_add_end_state(TAP_PD); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = NULL; switch (size) { case 4: fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32; break; case 2: fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16; break; case 1: fields[0].in_handler = arm_jtag_buf_to_8; break; } fields[0].in_handler_priv = in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[1].device = jtag_info->chain_pos; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[2].device = jtag_info->chain_pos; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1, NULL); jtag_add_runtest(0, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { jtag_execute_queue(); if (in) { DEBUG("in: 0x%8.8x", *in); } else { ERROR("BUG: called with in == NULL"); } } #endif return ERROR_OK; }
/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed) { scan_field_t fields[3]; u8 out_buf[4]; u8 instr_buf[4]; u8 sysspeed_buf = 0x0; /* prepare buffer */ buf_set_u32(out_buf, 0, 32, out); buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); jtag_add_end_state(TAP_PD); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; fields[0].out_value = out_buf; fields[0].out_mask = NULL; fields[0].in_value = NULL; if (in) { fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = in; } else { fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; } fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[1].device = jtag_info->chain_pos; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].device = jtag_info->chain_pos; fields[2].num_bits = 32; fields[2].out_value = instr_buf; fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1, NULL); jtag_add_runtest(0, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { jtag_execute_queue(); if (in) { DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); } else DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out); } #endif return ERROR_OK; }
int arm9tdmi_examine_debug_reason(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { scan_field_t fields[3]; u8 databus[4]; u8 instructionbus[4]; u8 debug_reason; jtag_add_end_state(TAP_PD); fields[0].device = arm7_9->jtag_info.chain_pos; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = databus; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; fields[1].device = arm7_9->jtag_info.chain_pos; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].out_mask = NULL; fields[1].in_value = &debug_reason; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[2].device = arm7_9->jtag_info.chain_pos; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].out_mask = NULL; fields[2].in_value = instructionbus; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; arm_jtag_scann(&arm7_9->jtag_info, 0x1); arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); jtag_add_dr_scan(3, fields, TAP_PD, NULL); jtag_execute_queue(); fields[0].in_value = NULL; fields[0].out_value = databus; fields[1].in_value = NULL; fields[1].out_value = &debug_reason; fields[2].in_value = NULL; fields[2].out_value = instructionbus; jtag_add_dr_scan(3, fields, TAP_PD, NULL); if (debug_reason & 0x4) if (debug_reason & 0x2) target->debug_reason = DBG_REASON_WPTANDBKPT; else target->debug_reason = DBG_REASON_WATCHPOINT; else target->debug_reason = DBG_REASON_BREAKPOINT; } return ERROR_OK; }
/* just read data (instruction and data-out = don't care) */ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) { int retval = ERROR_OK;; scan_field_t fields[3]; jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].out_mask = NULL; fields[2].in_value = NULL; fields[2].in_check_value = NULL; fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } if (in) { LOG_DEBUG("in: 0x%8.8x", *in); } else { LOG_ERROR("BUG: called with in == NULL"); } } #endif return ERROR_OK; }