static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time) { struct jz4740_rtc *rtc = dev_get_drvdata(dev); uint32_t secs, secs2; int timeout = 5; /* If the seconds register is read while it is updated, it can contain a * bogus value. This can be avoided by making sure that two consecutive * reads have the same value. */ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); while (secs != secs2 && --timeout) { secs = secs2; secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); } if (timeout == 0) return -EIO; rtc_time_to_tm(secs, time); return rtc_valid_tm(time); }
static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time) { struct jz4740_rtc *rtc = dev_get_drvdata(dev); uint32_t secs, secs2; int timeout = 5; /* */ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); while (secs != secs2 && --timeout) { secs = secs2; secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC); } if (timeout == 0) return -EIO; rtc_time_to_tm(secs, time); return rtc_valid_tm(time); }
static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask, bool set) { int ret; unsigned long flags; uint32_t ctrl; spin_lock_irqsave(&rtc->lock, flags); ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); /* Don't clear interrupt flags by accident */ ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF; if (set) ctrl |= mask; else ctrl &= ~mask; ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl); spin_unlock_irqrestore(&rtc->lock, flags); return ret; }
static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) { struct jz4740_rtc *rtc = dev_get_drvdata(dev); uint32_t secs; uint32_t ctrl; secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM); ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE); alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF); rtc_time_to_tm(secs, &alrm->time); return rtc_valid_tm(&alrm->time); }
static int jz4740_rtc_probe(struct platform_device *pdev) { int ret; struct jz4740_rtc *rtc; uint32_t scratchpad; struct resource *mem; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); if (!rtc) return -ENOMEM; rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) { dev_err(&pdev->dev, "Failed to get platform irq\n"); return -ENOENT; } mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(rtc->base)) return PTR_ERR(rtc->base); spin_lock_init(&rtc->lock); platform_set_drvdata(pdev, rtc); device_init_wakeup(&pdev->dev, 1); rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &jz4740_rtc_ops, THIS_MODULE); if (IS_ERR(rtc->rtc)) { ret = PTR_ERR(rtc->rtc); dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret); return ret; } ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0, pdev->name, rtc); if (ret) { dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret); return ret; } scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD); if (scratchpad != 0x12345678) { ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678); ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0); if (ret) { dev_err(&pdev->dev, "Could not write write to RTC registers\n"); return ret; } } return 0; }
static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc) { uint32_t ctrl; int timeout = 1000; do { ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); return timeout ? 0 : -EIO; }
static irqreturn_t jz4740_rtc_irq(int irq, void *data) { struct jz4740_rtc *rtc = data; uint32_t ctrl; unsigned long events = 0; ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); if (ctrl & JZ_RTC_CTRL_1HZ) events |= (RTC_UF | RTC_IRQF); if (ctrl & JZ_RTC_CTRL_AF) events |= (RTC_AF | RTC_IRQF); rtc_update_irq(rtc->rtc, 1, events); jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false); return IRQ_HANDLED; }
static int jz4740_rtc_probe(struct platform_device *pdev) { int ret; struct jz4740_rtc *rtc; uint32_t scratchpad; struct resource *mem; const struct platform_device_id *id = platform_get_device_id(pdev); const struct of_device_id *of_id = of_match_device( jz4740_rtc_of_match, &pdev->dev); struct device_node *np = pdev->dev.of_node; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); if (!rtc) return -ENOMEM; if (of_id) rtc->type = (enum jz4740_rtc_type)of_id->data; else rtc->type = id->driver_data; rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) { dev_err(&pdev->dev, "Failed to get platform irq\n"); return -ENOENT; } mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(rtc->base)) return PTR_ERR(rtc->base); rtc->clk = devm_clk_get(&pdev->dev, "rtc"); if (IS_ERR(rtc->clk)) { dev_err(&pdev->dev, "Failed to get RTC clock\n"); return PTR_ERR(rtc->clk); } spin_lock_init(&rtc->lock); platform_set_drvdata(pdev, rtc); device_init_wakeup(&pdev->dev, 1); rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &jz4740_rtc_ops, THIS_MODULE); if (IS_ERR(rtc->rtc)) { ret = PTR_ERR(rtc->rtc); dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret); return ret; } ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0, pdev->name, rtc); if (ret) { dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret); return ret; } scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD); if (scratchpad != 0x12345678) { ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678); ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0); if (ret) { dev_err(&pdev->dev, "Could not write write to RTC registers\n"); return ret; } } if (np && of_device_is_system_power_controller(np)) { if (!pm_power_off) { /* Default: 60ms */ rtc->reset_pin_assert_time = 60; of_property_read_u32(np, "reset-pin-assert-time-ms", &rtc->reset_pin_assert_time); /* Default: 100ms */ rtc->min_wakeup_pin_assert_time = 100; of_property_read_u32(np, "min-wakeup-pin-assert-time-ms", &rtc->min_wakeup_pin_assert_time); dev_for_power_off = &pdev->dev; pm_power_off = jz4740_rtc_power_off; } else { dev_warn(&pdev->dev, "Poweroff handler already present!\n"); } } return 0; }
static int __devinit jz4740_rtc_probe(struct platform_device *pdev) { int ret; struct jz4740_rtc *rtc; uint32_t scratchpad; rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); if (!rtc) return -ENOMEM; rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) { ret = -ENOENT; dev_err(&pdev->dev, "Failed to get platform irq\n"); goto err_free; } rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!rtc->mem) { ret = -ENOENT; dev_err(&pdev->dev, "Failed to get platform mmio memory\n"); goto err_free; } rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem), pdev->name); if (!rtc->mem) { ret = -EBUSY; dev_err(&pdev->dev, "Failed to request mmio memory region\n"); goto err_free; } rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem)); if (!rtc->base) { ret = -EBUSY; dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); goto err_release_mem_region; } spin_lock_init(&rtc->lock); platform_set_drvdata(pdev, rtc); device_init_wakeup(&pdev->dev, 1); rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops, THIS_MODULE); if (IS_ERR(rtc->rtc)) { ret = PTR_ERR(rtc->rtc); dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret); goto err_iounmap; } ret = request_irq(rtc->irq, jz4740_rtc_irq, 0, pdev->name, rtc); if (ret) { dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret); goto err_unregister_rtc; } scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD); if (scratchpad != 0x12345678) { ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678); ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0); if (ret) { dev_err(&pdev->dev, "Could not write write to RTC registers\n"); goto err_free_irq; } } return 0; err_free_irq: free_irq(rtc->irq, rtc); err_unregister_rtc: rtc_device_unregister(rtc->rtc); err_iounmap: platform_set_drvdata(pdev, NULL); iounmap(rtc->base); err_release_mem_region: release_mem_region(rtc->mem->start, resource_size(rtc->mem)); err_free: kfree(rtc); return ret; }