static int adc_sam_initialize(struct device *dev)
{
const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
/* Initialize semaphores */
k_sem_init(&dev_data->sem_meas, 0, 1);
k_sem_init(&dev_data->mutex_thread, 1, 1);
/* Configure interrupts */
dev_cfg->irq_config();
/* Enable module's clock */
soc_pmc_peripheral_enable(dev_cfg->periph_id);
/* Configure ADC */
adc_sam_configure(dev);
/* Enable module interrupt */
irq_enable(dev_cfg->irq_id);
SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
return 0;
}
static int i2s_stm32_initialize(struct device *dev)
{
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
int ret, i;
/* Enable I2S clock propagation */
ret = i2s_stm32_enable_clock(dev);
if (ret < 0) {
LOG_ERR("%s: clock enabling failed: %d", __func__, ret);
return -EIO;
}
cfg->irq_config(dev);
k_sem_init(&dev_data->rx.sem, 0, CONFIG_I2S_STM32_RX_BLOCK_COUNT);
k_sem_init(&dev_data->tx.sem, CONFIG_I2S_STM32_TX_BLOCK_COUNT,
CONFIG_I2S_STM32_TX_BLOCK_COUNT);
for (i = 0; i < STM32_DMA_NUM_CHANNELS; i++) {
active_dma_rx_channel[i] = NULL;
active_dma_tx_channel[i] = NULL;
}
/* Get the binding to the DMA device */
dev_data->dev_dma = device_get_binding(dev_data->dma_name);
if (!dev_data->dev_dma) {
LOG_ERR("%s device not found", dev_data->dma_name);
return -ENODEV;
}
LOG_INF("%s inited", dev->config->name);
return 0;
}
static int nrf5_init(struct device *dev)
{
const struct nrf5_802154_config *nrf5_radio_cfg = NRF5_802154_CFG(dev);
struct nrf5_802154_data *nrf5_radio = NRF5_802154_DATA(dev);
struct device *clk_m16;
k_sem_init(&nrf5_radio->rx_wait, 0, 1);
k_sem_init(&nrf5_radio->tx_wait, 0, 1);
k_sem_init(&nrf5_radio->cca_wait, 0, 1);
clk_m16 = device_get_binding(CONFIG_CLOCK_CONTROL_NRF5_M16SRC_DRV_NAME);
if (!clk_m16) {
return -ENODEV;
}
clock_control_on(clk_m16, NULL);
nrf_drv_radio802154_init();
nrf5_radio_cfg->irq_config_func(dev);
k_thread_create(&nrf5_radio->rx_thread, nrf5_radio->rx_stack,
CONFIG_IEEE802154_NRF5_RX_STACK_SIZE,
nrf5_rx_thread, dev, NULL, NULL,
K_PRIO_COOP(2), 0, 0);
SYS_LOG_INF("nRF5 802154 radio initialized");
return 0;
}
static int entropy_nrf5_init(struct device *device)
{
/* Check if this API is called on correct driver instance. */
__ASSERT_NO_MSG(&entropy_nrf5_data == DEV_DATA(device));
/* Locking semaphore initialized to 1 (unlocked) */
k_sem_init(&entropy_nrf5_data.sem_lock, 1, 1);
/* Synching semaphore */
k_sem_init(&entropy_nrf5_data.sem_sync, 0, 1);
rng_pool_init((struct rng_pool *)(entropy_nrf5_data.thr),
CONFIG_ENTROPY_NRF5_THR_POOL_SIZE,
CONFIG_ENTROPY_NRF5_THR_THRESHOLD);
rng_pool_init((struct rng_pool *)(entropy_nrf5_data.isr),
CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE,
CONFIG_ENTROPY_NRF5_ISR_THRESHOLD);
/* Enable or disable bias correction */
if (IS_ENABLED(CONFIG_ENTROPY_NRF5_BIAS_CORRECTION)) {
nrf_rng_error_correction_enable();
} else {
nrf_rng_error_correction_disable();
}
nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
nrf_rng_int_enable(NRF_RNG_INT_VALRDY_MASK);
nrf_rng_task_trigger(NRF_RNG_TASK_START);
IRQ_CONNECT(RNG_IRQn, CONFIG_ENTROPY_NRF5_PRI, isr,
&entropy_nrf5_data, 0);
irq_enable(RNG_IRQn);
return 0;
}
static void test_objects_init(void)
{
k_sem_init(&test_thread_sem, 0, UINT_MAX);
k_sem_init(&helper_thread_sem, 0, UINT_MAX);
k_sem_init(&task_sem, 0, UINT_MAX);
TC_PRINT("Kernel objects initialized\n");
}
/**
*
* @brief Initialize kernel objects
*
* This routine initializes the kernel objects used in this module's tests.
*
* @return TC_PASS
*/
static int kernel_init_objects(void)
{
k_sem_init(&sem_thread, 0, UINT_MAX);
k_sem_init(&reply_timeout, 0, UINT_MAX);
k_timer_init(&timer, NULL, NULL);
k_fifo_init(&timeout_order_fifo);
return TC_PASS;
}
static int i2c_qmsi_init(struct device *dev)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
const struct i2c_qmsi_config_info *config = dev->config->config_info;
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
u32_t bitrate_cfg;
int err;
k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
k_sem_init(&driver_data->sem, 1, UINT_MAX);
switch (instance) {
case QM_I2C_0:
/* Register interrupt handler, unmask IRQ and route it
* to Lakemont core.
*/
IRQ_CONNECT(CONFIG_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
CONFIG_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
break;
#ifdef CONFIG_I2C_1
case QM_I2C_1:
IRQ_CONNECT(CONFIG_I2C_1_IRQ,
CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
CONFIG_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
break;
#endif /* CONFIG_I2C_1 */
default:
return -EIO;
}
clk_periph_enable(config->clock_gate);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (err < 0) {
return err;
}
dev->driver_api = &api;
i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
void test_arm_irq_vector_table(void)
{
printk("Test Cortex-M3 IRQ installed directly in vector table\n");
for (int ii = 0; ii < 3; ii++) {
irq_enable(ii);
_irq_priority_set(ii, 0, 0);
k_sem_init(&sem[ii], 0, UINT_MAX);
}
zassert_true((k_sem_take(&sem[0], K_NO_WAIT) ||
k_sem_take(&sem[1], K_NO_WAIT) ||
k_sem_take(&sem[2], K_NO_WAIT)), NULL);
for (int ii = 0; ii < 3; ii++) {
#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
/* the QEMU does not simulate the
* STIR register: this is a workaround
*/
NVIC_SetPendingIRQ(ii);
#else
NVIC->STIR = ii;
#endif
}
zassert_false((k_sem_take(&sem[0], K_NO_WAIT) ||
k_sem_take(&sem[1], K_NO_WAIT) ||
k_sem_take(&sem[2], K_NO_WAIT)), NULL);
}
static int mcux_elcdif_init(struct device *dev)
{
const struct mcux_elcdif_config *config = dev->config->config_info;
struct mcux_elcdif_data *data = dev->driver_data;
int i;
elcdif_rgb_mode_config_t rgb_mode = config->rgb_mode;
data->pixel_bytes = config->bits_per_pixel / 8U;
data->fb_bytes = data->pixel_bytes *
rgb_mode.panelWidth * rgb_mode.panelHeight;
data->write_idx = 1U;
for (i = 0; i < ARRAY_SIZE(data->fb); i++) {
if (k_mem_pool_alloc(&mcux_elcdif_pool, &data->fb[i],
data->fb_bytes, K_NO_WAIT) != 0) {
LOG_ERR("Could not allocate frame buffer %d", i);
return -ENOMEM;
}
memset(data->fb[i].data, 0, data->fb_bytes);
}
rgb_mode.bufferAddr = (uint32_t) data->fb[0].data;
k_sem_init(&data->sem, 1, 1);
config->irq_config_func(dev);
ELCDIF_RgbModeInit(config->base, &rgb_mode);
ELCDIF_EnableInterrupts(config->base,
kELCDIF_CurFrameDoneInterruptEnable);
ELCDIF_RgbModeStart(config->base);
return 0;
}
STATIC mp_obj_t mod_getaddrinfo(size_t n_args, const mp_obj_t *args) {
mp_obj_t host_in = args[0], port_in = args[1];
const char *host = mp_obj_str_get_str(host_in);
mp_int_t family = 0;
if (n_args > 2) {
family = mp_obj_get_int(args[2]);
}
getaddrinfo_state_t state;
// Just validate that it's int
(void)mp_obj_get_int(port_in);
state.port = port_in;
state.result = mp_obj_new_list(0, NULL);
k_sem_init(&state.sem, 0, UINT_MAX);
for (int i = 2; i--;) {
int type = (family != AF_INET6 ? DNS_QUERY_TYPE_A : DNS_QUERY_TYPE_AAAA);
RAISE_ERRNO(dns_get_addr_info(host, type, NULL, dns_resolve_cb, &state, 3000));
k_sem_take(&state.sem, K_FOREVER);
if (family != 0) {
break;
}
family = AF_INET6;
}
// Raise error only if there's nothing to return, otherwise
// it may be IPv4 vs IPv6 differences.
mp_int_t len = MP_OBJ_SMALL_INT_VALUE(mp_obj_len(state.result));
if (state.status != 0 && len == 0) {
mp_raise_OSError(state.status);
}
return state.result;
}
static int start_https(struct http_client_ctx *ctx)
{
struct k_sem startup_sync;
/* Start the thread that handles HTTPS traffic. */
if (ctx->https.tid) {
return -EALREADY;
}
NET_DBG("Starting HTTPS thread for %p", ctx);
k_sem_init(&startup_sync, 0, 1);
ctx->https.tid = k_thread_create(&ctx->https.thread,
ctx->https.stack,
ctx->https.stack_size,
(k_thread_entry_t)https_handler,
ctx, &startup_sync, 0,
K_PRIO_COOP(7), 0, 0);
/* Wait until we know that the HTTPS thread startup was ok */
if (k_sem_take(&startup_sync, HTTPS_STARTUP_TIMEOUT) < 0) {
https_shutdown(ctx);
return -ECANCELED;
}
NET_DBG("HTTPS thread %p started for %p", ctx->https.tid, ctx);
return 0;
}
static int resolve_name(struct http_client_ctx *ctx,
const char *server,
enum dns_query_type type)
{
struct waiter dns_waiter;
int ret;
dns_waiter.ctx = ctx;
k_sem_init(&dns_waiter.wait, 0, 1);
ret = dns_get_addr_info(server, type, &ctx->dns_id, dns_cb,
&dns_waiter, DNS_WAIT);
if (ret < 0) {
NET_ERR("Cannot resolve %s (%d)", server, ret);
ctx->dns_id = 0;
return ret;
}
/* Wait a little longer for the DNS to finish so that
* the DNS will timeout before the semaphore.
*/
if (k_sem_take(&dns_waiter.wait, DNS_WAIT_SEM)) {
NET_ERR("Timeout while resolving %s", server);
ctx->dns_id = 0;
return -ETIMEDOUT;
}
ctx->dns_id = 0;
if (ctx->tcp.remote.family == AF_UNSPEC) {
return -EINVAL;
}
return 0;
}
static int i2c_mcux_init(struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = DEV_CFG(dev);
struct i2c_mcux_data *data = DEV_DATA(dev);
u32_t clock_freq, bitrate_cfg;
i2c_master_config_t master_config;
int error;
k_sem_init(&data->device_sync_sem, 0, UINT_MAX);
clock_freq = CLOCK_GetFreq(config->clock_source);
I2C_MasterGetDefaultConfig(&master_config);
I2C_MasterInit(base, &master_config, clock_freq);
I2C_MasterTransferCreateHandle(base, &data->handle,
i2c_mcux_master_transfer_callback, dev);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
error = i2c_mcux_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (error) {
return error;
}
config->irq_config_func(dev);
return 0;
}
int bmg160_init(struct device *dev)
{
const struct bmg160_device_config *cfg = dev->config->config_info;
struct bmg160_device_data *bmg160 = dev->driver_data;
u8_t chip_id = 0;
u16_t range_dps;
bmg160->i2c = device_get_binding((char *)cfg->i2c_port);
if (!bmg160->i2c) {
SYS_LOG_DBG("I2C master controller not found!");
return -EINVAL;
}
k_sem_init(&bmg160->sem, 1, UINT_MAX);
if (bmg160_read_byte(dev, BMG160_REG_CHIPID, &chip_id) < 0) {
SYS_LOG_DBG("Failed to read chip id.");
return -EIO;
}
if (chip_id != BMG160_CHIP_ID) {
SYS_LOG_DBG("Unsupported chip detected (0x%x)!", chip_id);
return -ENODEV;
}
/* reset the chip */
bmg160_write_byte(dev, BMG160_REG_BGW_SOFTRESET, BMG160_RESET);
k_busy_wait(1000); /* wait for the chip to come up */
if (bmg160_write_byte(dev, BMG160_REG_RANGE,
BMG160_DEFAULT_RANGE) < 0) {
SYS_LOG_DBG("Failed to set range.");
return -EIO;
}
range_dps = bmg160_gyro_range_map[BMG160_DEFAULT_RANGE];
bmg160->scale = BMG160_RANGE_TO_SCALE(range_dps);
if (bmg160_write_byte(dev, BMG160_REG_BW, BMG160_DEFAULT_ODR) < 0) {
SYS_LOG_DBG("Failed to set sampling frequency.");
return -EIO;
}
/* disable interrupts */
if (bmg160_write_byte(dev, BMG160_REG_INT_EN0, 0) < 0) {
SYS_LOG_DBG("Failed to disable all interrupts.");
return -EIO;
}
#ifdef CONFIG_BMG160_TRIGGER
bmg160_trigger_init(dev);
#endif
dev->driver_api = &bmg160_api;
return 0;
}
int bmg160_trigger_init(struct device *dev)
{
const struct bmg160_device_config *cfg = dev->config->config_info;
struct bmg160_device_data *bmg160 = dev->driver_data;
/* set INT1 pin to: push-pull, active low */
if (bmg160_write_byte(dev, BMG160_REG_INT_EN1, 0) < 0) {
SYS_LOG_DBG("Failed to select interrupt pins type.");
return -EIO;
}
/* set interrupt mode to non-latched */
if (bmg160_write_byte(dev, BMG160_REG_INT_RST_LATCH, 0) < 0) {
SYS_LOG_DBG("Failed to set the interrupt mode.");
return -EIO;
}
/* map anymotion and high rate interrupts to INT1 pin */
if (bmg160_write_byte(dev, BMG160_REG_INT_MAP0,
BMG160_INT1_ANY | BMG160_INT1_HIGH) < 0) {
SYS_LOG_DBG("Unable to map interrupts.");
return -EIO;
}
/* map data ready, FIFO and FastOffset interrupts to INT1 pin */
if (bmg160_write_byte(dev, BMG160_REG_INT_MAP1,
BMG160_INT1_DATA | BMG160_INT1_FIFO |
BMG160_INT1_FAST_OFFSET) < 0) {
SYS_LOG_DBG("Unable to map interrupts.");
return -EIO;
}
bmg160->gpio = device_get_binding((char *)cfg->gpio_port);
if (!bmg160->gpio) {
SYS_LOG_DBG("Gpio controller %s not found", cfg->gpio_port);
return -EINVAL;
}
#if defined(CONFIG_BMG160_TRIGGER_OWN_THREAD)
k_sem_init(&bmg160->trig_sem, 0, UINT_MAX);
k_thread_create(&bmg160_thread, bmg160_thread_stack,
CONFIG_BMG160_THREAD_STACK_SIZE, bmg160_thread_main,
dev, NULL, NULL, K_PRIO_COOP(10), 0, 0);
#elif defined(CONFIG_BMG160_TRIGGER_GLOBAL_THREAD)
bmg160->work.handler = bmg160_work_cb;
bmg160->dev = dev;
#endif
gpio_pin_configure(bmg160->gpio, cfg->int_pin,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_LOW | GPIO_INT_DEBOUNCE);
gpio_init_callback(&bmg160->gpio_cb, bmg160_gpio_callback,
BIT(cfg->int_pin));
gpio_add_callback(bmg160->gpio, &bmg160->gpio_cb);
gpio_pin_enable_callback(bmg160->gpio, cfg->int_pin);
return 0;
}
static void l2cap_chan_tx_init(struct bt_l2cap_le_chan *chan)
{
BT_DBG("chan %p", chan);
memset(&chan->tx, 0, sizeof(chan->tx));
k_sem_init(&chan->tx.credits, 0, UINT_MAX);
k_fifo_init(&chan->tx_queue,"",NULL,10);
}
int udp_init(struct udp_context *ctx)
{
struct net_context *udp_ctx = { 0 };
struct net_context *mcast_ctx = { 0 };
struct sockaddr_in6 my_addr = { 0 };
struct sockaddr_in6 my_mcast_addr = { 0 };
int rc;
k_sem_init(&ctx->rx_sem, 0, UINT_MAX);
net_ipaddr_copy(&my_mcast_addr.sin6_addr, &mcast_addr);
my_mcast_addr.sin6_family = AF_INET6;
net_ipaddr_copy(&my_addr.sin6_addr, &server_addr);
my_addr.sin6_family = AF_INET6;
my_addr.sin6_port = htons(SERVER_PORT);
rc = net_context_get(AF_INET6, SOCK_DGRAM, IPPROTO_UDP, &udp_ctx);
if (rc < 0) {
printk("Cannot get network context for IPv6 UDP (%d)", rc);
return -EIO;
}
rc = net_context_bind(udp_ctx, (struct sockaddr *)&my_addr,
sizeof(struct sockaddr_in6));
if (rc < 0) {
printk("Cannot bind IPv6 UDP port %d (%d)", SERVER_PORT, rc);
goto error;
}
rc = net_context_get(AF_INET6, SOCK_DGRAM, IPPROTO_UDP, &mcast_ctx);
if (rc < 0) {
printk("Cannot get receiving IPv6 mcast (%d)", rc);
goto error;
}
rc = net_context_bind(mcast_ctx, (struct sockaddr *)&my_mcast_addr,
sizeof(struct sockaddr_in6));
if (rc < 0) {
printk("Cannot get bind IPv6 mcast (%d)", rc);
goto error;
}
ctx->rx_pkt = NULL;
ctx->remaining = 0;
ctx->net_ctx = udp_ctx;
rc = net_context_recv(ctx->net_ctx, udp_received, K_NO_WAIT, ctx);
if (rc != 0) {
return -EIO;
}
return 0;
error:
net_context_put(udp_ctx);
return -EINVAL;
}
void test_sema_thread2isr(void)
{
/**TESTPOINT: test k_sem_init sema*/
k_sem_init(&sema, SEM_INITIAL, SEM_LIMIT);
tsema_thread_isr(&sema);
/**TESTPOINT: test K_SEM_DEFINE sema*/
tsema_thread_isr(&ksema);
}
static int rtc_stm32_init(struct device *dev)
{
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
const struct rtc_stm32_config *cfg = DEV_CFG(dev);
__ASSERT_NO_MSG(clk);
k_sem_init(DEV_SEM(dev), 1, UINT_MAX);
DEV_DATA(dev)->cb_fn = NULL;
clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
LL_PWR_EnableBkUpAccess();
LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset();
#if defined(CONFIG_RTC_STM32_CLOCK_LSI)
LL_RCC_LSI_Enable();
while (LL_RCC_LSI_IsReady() != 1)
;
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);
#else /* CONFIG_RTC_STM32_CLOCK_LSE */
LL_RCC_LSE_SetDriveCapability(CONFIG_RTC_STM32_LSE_DRIVE_STRENGTH);
LL_RCC_LSE_Enable();
/* Wait untill LSE is ready */
while (LL_RCC_LSE_IsReady() != 1)
;
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
#endif /* CONFIG_RTC_STM32_CLOCK_SRC */
LL_RCC_EnableRTC();
if (LL_RTC_DeInit(RTC) != SUCCESS) {
return -EIO;
}
if (LL_RTC_Init(RTC, ((LL_RTC_InitTypeDef *)
&cfg->ll_rtc_config)) != SUCCESS) {
return -EIO;
}
LL_RTC_EnableShadowRegBypass(RTC);
LL_EXTI_EnableIT_0_31(EXTI_LINE);
LL_EXTI_EnableRisingTrig_0_31(EXTI_LINE);
rtc_stm32_irq_config(dev);
return 0;
}
static void init_tx_queue(void)
{
k_sem_init(&tx_sem, 0, UINT_MAX);
k_fifo_init(&tx_queue);
k_thread_create(&tx_thread_data, tx_stack,
K_THREAD_STACK_SIZEOF(tx_stack),
(k_thread_entry_t)tx_thread,
NULL, NULL, NULL, K_PRIO_COOP(8), 0, K_NO_WAIT);
}
void test_call_stacks_analyze_workq(void)
{
TC_PRINT("from workq:\n");
k_sem_init(&sync_sema, 0, NUM_OF_WORK);
for (int i = 0; i < NUM_OF_WORK; i++) {
k_work_init(&work[i], work_handler);
k_work_submit(&work[i]);
k_sem_take(&sync_sema, K_FOREVER);
}
}
static void tstack_thread_isr(struct k_stack *pstack)
{
k_sem_init(&end_sema, 0, 1);
/**TESTPOINT: thread-isr data passing via stack*/
irq_offload(tIsr_entry_push, pstack);
tstack_pop(pstack);
tstack_push(pstack);
irq_offload(tIsr_entry_pop, pstack);
}
static int queue_init(Gmac *gmac, struct gmac_queue *queue)
{
int result;
__ASSERT_NO_MSG(queue->rx_desc_list.len > 0);
__ASSERT_NO_MSG(queue->tx_desc_list.len > 0);
__ASSERT(!((u32_t)queue->rx_desc_list.buf & ~GMAC_RBQB_ADDR_Msk),
"RX descriptors have to be word aligned");
__ASSERT(!((u32_t)queue->tx_desc_list.buf & ~GMAC_TBQB_ADDR_Msk),
"TX descriptors have to be word aligned");
/* Setup descriptor lists */
result = rx_descriptors_init(gmac, queue);
if (result < 0) {
return result;
}
tx_descriptors_init(gmac, queue);
/* Initialize TX descriptors semaphore. The semaphore is required as the
* size of the TX descriptor list is limited while the number of TX data
* buffers is not.
*/
k_sem_init(&queue->tx_desc_sem, queue->tx_desc_list.len - 1,
queue->tx_desc_list.len - 1);
/* Set Receive Buffer Queue Pointer Register */
gmac->GMAC_RBQB = (u32_t)queue->rx_desc_list.buf;
/* Set Transmit Buffer Queue Pointer Register */
gmac->GMAC_TBQB = (u32_t)queue->tx_desc_list.buf;
/* Configure GMAC DMA transfer */
gmac->GMAC_DCFGR =
/* Receive Buffer Size (defined in multiples of 64 bytes) */
GMAC_DCFGR_DRBS(CONFIG_NET_BUF_DATA_SIZE >> 6)
/* 4 kB Receiver Packet Buffer Memory Size */
| GMAC_DCFGR_RXBMS_FULL
/* 4 kB Transmitter Packet Buffer Memory Size */
| GMAC_DCFGR_TXPBMS
/* Transmitter Checksum Generation Offload Enable */
| GMAC_DCFGR_TXCOEN
/* Attempt to use INCR4 AHB bursts (Default) */
| GMAC_DCFGR_FBLDO_INCR4;
/* Setup RX/TX completion and error interrupts */
gmac->GMAC_IER = GMAC_INT_EN_FLAGS;
queue->err_rx_frames_dropped = 0;
queue->err_rx_flushed_count = 0;
queue->err_tx_flushed_count = 0;
SYS_LOG_INF("Queue %d activated", queue->que_idx);
return 0;
}
static int spi_qmsi_init(struct device *dev)
{
const struct spi_qmsi_config *spi_config = dev->config->config_info;
struct spi_qmsi_runtime *context = dev->driver_data;
switch (spi_config->spi) {
case QM_SPI_MST_0:
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT),
CONFIG_SPI_0_IRQ_PRI, qm_spi_master_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT));
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->spi_master_0_int_mask);
break;
#ifdef CONFIG_SPI_1
case QM_SPI_MST_1:
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT),
CONFIG_SPI_1_IRQ_PRI, qm_spi_master_1_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT));
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->spi_master_1_int_mask);
break;
#endif /* CONFIG_SPI_1 */
default:
return -EIO;
}
context->gpio_cs = gpio_cs_init(spi_config);
k_sem_init(&context->device_sync_sem, 0, UINT_MAX);
k_sem_init(&context->sem, 1, UINT_MAX);
spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
dev->driver_api = &spi_qmsi_api;
return 0;
}
/*test cases*/
void test_sema_thread2thread(void)
{
struct k_sem sema;
/**TESTPOINT: test k_sem_init sema*/
k_sem_init(&sema, SEM_INITIAL, SEM_LIMIT);
tsema_thread_thread(&sema);
/**TESTPOINT: test K_SEM_DEFINE sema*/
tsema_thread_thread(&ksema);
}
int lsm6dsl_init_interrupt(struct device *dev)
{
struct lsm6dsl_data *drv_data = dev->driver_data;
/* setup data ready gpio interrupt */
drv_data->gpio = device_get_binding(CONFIG_LSM6DSL_GPIO_DEV_NAME);
if (drv_data->gpio == NULL) {
SYS_LOG_ERR("Cannot get pointer to %s device.",
CONFIG_LSM6DSL_GPIO_DEV_NAME);
return -EINVAL;
}
gpio_pin_configure(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
gpio_init_callback(&drv_data->gpio_cb,
lsm6dsl_gpio_callback,
BIT(CONFIG_LSM6DSL_GPIO_PIN_NUM));
if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) {
SYS_LOG_ERR("Could not set gpio callback.");
return -EIO;
}
/* enable data-ready interrupt */
if (drv_data->hw_tf->update_reg(drv_data,
LSM6DSL_REG_INT1_CTRL,
LSM6DSL_SHIFT_INT1_CTRL_DRDY_XL |
LSM6DSL_SHIFT_INT1_CTRL_DRDY_G,
(1 << LSM6DSL_SHIFT_INT1_CTRL_DRDY_XL) |
(1 << LSM6DSL_SHIFT_INT1_CTRL_DRDY_G)) < 0) {
SYS_LOG_ERR("Could not enable data-ready interrupt.");
return -EIO;
}
#if defined(CONFIG_LSM6DSL_TRIGGER_OWN_THREAD)
k_sem_init(&drv_data->gpio_sem, 0, UINT_MAX);
k_thread_create(&drv_data->thread, drv_data->thread_stack,
CONFIG_LSM6DSL_THREAD_STACK_SIZE,
(k_thread_entry_t)lsm6dsl_thread, dev,
0, NULL, K_PRIO_COOP(CONFIG_LSM6DSL_THREAD_PRIORITY),
0, 0);
#elif defined(CONFIG_LSM6DSL_TRIGGER_GLOBAL_THREAD)
drv_data->work.handler = lsm6dsl_work_cb;
drv_data->dev = dev;
#endif
gpio_pin_enable_callback(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM);
return 0;
}
int lis2dw12_init_interrupt(struct device *dev)
{
struct lis2dw12_data *lis2dw12 = dev->driver_data;
const struct lis2dw12_device_config *cfg = dev->config->config_info;
int ret;
/* setup data ready gpio interrupt (INT1 or INT2) */
lis2dw12->gpio = device_get_binding(cfg->int_gpio_port);
if (lis2dw12->gpio == NULL) {
LOG_DBG("Cannot get pointer to %s device",
cfg->int_gpio_port);
return -EINVAL;
}
#if defined(CONFIG_LIS2DW12_TRIGGER_OWN_THREAD)
k_sem_init(&lis2dw12->gpio_sem, 0, UINT_MAX);
k_thread_create(&lis2dw12->thread, lis2dw12->thread_stack,
CONFIG_LIS2DW12_THREAD_STACK_SIZE,
(k_thread_entry_t)lis2dw12_thread, dev,
0, NULL, K_PRIO_COOP(CONFIG_LIS2DW12_THREAD_PRIORITY),
0, 0);
#elif defined(CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD)
lis2dw12->work.handler = lis2dw12_work_cb;
lis2dw12->dev = dev;
#endif /* CONFIG_LIS2DW12_TRIGGER_OWN_THREAD */
ret = gpio_pin_configure(lis2dw12->gpio, cfg->int_gpio_pin,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
if (ret < 0) {
LOG_DBG("Could not configure gpio");
return ret;
}
gpio_init_callback(&lis2dw12->gpio_cb,
lis2dw12_gpio_callback,
BIT(cfg->int_gpio_pin));
if (gpio_add_callback(lis2dw12->gpio, &lis2dw12->gpio_cb) < 0) {
LOG_DBG("Could not set gpio callback");
return -EIO;
}
/* enable interrupt on int1/int2 in pulse mode */
if (lis2dw12->hw_tf->update_reg(lis2dw12, LIS2DW12_CTRL3_ADDR,
LIS2DW12_LIR_MASK, LIS2DW12_DIS_BIT)) {
return -EIO;
}
return gpio_pin_enable_callback(lis2dw12->gpio, cfg->int_gpio_pin);
}
void test_sema_reset(void)
{
k_sem_init(&sema, SEM_INITIAL, SEM_LIMIT);
k_sem_give(&sema);
k_sem_reset(&sema);
zassert_false(k_sem_count_get(&sema), NULL);
/**TESTPOINT: sem take return -EBUSY*/
zassert_equal(k_sem_take(&sema, K_NO_WAIT), -EBUSY, NULL);
/**TESTPOINT: sem take return -EAGAIN*/
zassert_equal(k_sem_take(&sema, TIMEOUT), -EAGAIN, NULL);
k_sem_give(&sema);
zassert_false(k_sem_take(&sema, K_FOREVER), NULL);
}
static int stm32_flash_init(struct device *dev)
{
struct flash_stm32_priv *p = dev->driver_data;
#if defined(CONFIG_SOC_SERIES_STM32L4X)
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
/* enable clock */
clock_control_on(clk, (clock_control_subsys_t *)&p->pclken);
#endif
k_sem_init(&p->sem, 1, 1);
return flash_stm32_write_protection(dev, false);
}
static int i2c_dw_initialize(struct device *dev)
{
const struct i2c_dw_rom_config * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers *regs;
if (!i2c_dw_pci_setup(dev)) {
dev->driver_api = NULL;
return -EIO;
}
k_sem_init(&dw->device_sync_sem, 0, UINT_MAX);
regs = (struct i2c_dw_registers *) dw->base_address;
/* verify that we have a valid DesignWare register first */
if (regs->ic_comp_type != I2C_DW_MAGIC_KEY) {
dev->driver_api = NULL;
SYS_LOG_DBG("I2C: DesignWare magic key not found, check base "
"address. Stopping initialization");
return -EIO;
}
/*
* grab the default value on initialization. This should be set to the
* IC_MAX_SPEED_MODE in the hardware. If it does support high speed we
* can move provide support for it
*/
if (regs->ic_con.bits.speed == I2C_DW_SPEED_HIGH) {
SYS_LOG_DBG("I2C: high speed supported");
dw->support_hs_mode = true;
} else {
SYS_LOG_DBG("I2C: high speed NOT supported");
dw->support_hs_mode = false;
}
rom->config_func(dev);
dw->app_config = I2C_MODE_MASTER | _i2c_map_dt_bitrate(rom->bitrate);
if (i2c_dw_runtime_configure(dev, dw->app_config) != 0) {
SYS_LOG_DBG("I2C: Cannot set default configuration");
return -EIO;
}
dw->state = I2C_DW_STATE_READY;
return 0;
}
