void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot, int *remain, int hang) { struct kgsl_device *device = &adreno_dev->dev; struct kgsl_snapshot_registers regs; regs.regs = (unsigned int *) a3xx_registers; regs.count = a3xx_registers_count; /* Master set of (non debug) registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain, kgsl_snapshot_dump_regs, ®s); /* CP_STATE_DEBUG indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_STATE_DEBUG_INDEX, REG_CP_STATE_DEBUG_DATA, 0x0, 0x14); /* CP_ME indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_ME_CNTL, REG_CP_ME_STATUS, 64, 44); /* VPC memory */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_vpc_memory, NULL); /* CP MEQ */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_meq, NULL); /* CP PFP and PM4 */ /* Reading these will hang the GPU if it isn't already hung */ if (hang) { snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pfp_ram, NULL); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pm4_ram, NULL); } /* CP ROQ */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_roq, NULL); snapshot = a3xx_snapshot_debugbus(device, snapshot, remain); return snapshot; }
void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot, int *remain, int hang) { struct kgsl_device *device = &adreno_dev->dev; struct kgsl_snapshot_registers_list list; struct kgsl_snapshot_registers regs[5]; list.registers = regs; list.count = 0; adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00); _snapshot_a3xx_regs(regs, &list); _snapshot_hlsq_regs(regs, &list, adreno_dev); if (adreno_is_a330(adreno_dev)) _snapshot_a330_regs(regs, &list); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain, kgsl_snapshot_dump_regs, &list); snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_STATE_DEBUG_INDEX, REG_CP_STATE_DEBUG_DATA, 0x0, 0x14); snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_ME_CNTL, REG_CP_ME_STATUS, 64, 44); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_vpc_memory, NULL); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_meq, NULL); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_shader_memory, NULL); if (hang) { snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pfp_ram, NULL); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pm4_ram, NULL); } snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_roq, NULL); if (adreno_is_a330(adreno_dev)) { snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a330_snapshot_cp_merciu, NULL); } snapshot = a3xx_snapshot_debugbus(device, snapshot, remain); adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, A3XX_RBBM_CLOCK_CTL_DEFAULT); return snapshot; }
void *a2xx_snapshot(struct adreno_device *adreno_dev, void *snapshot, int *remain, int hang) { struct kgsl_device *device = &adreno_dev->dev; struct kgsl_snapshot_registers_list list; struct kgsl_snapshot_registers regs; unsigned int pmoverride; /* Choose the register set to dump */ if (adreno_is_a20x(adreno_dev)) { regs.regs = (unsigned int *) a200_registers; regs.count = a200_registers_count; } else if (adreno_is_a220(adreno_dev)) { regs.regs = (unsigned int *) a220_registers; regs.count = a220_registers_count; } else if (adreno_is_a225(adreno_dev)) { regs.regs = (unsigned int *) a225_registers; regs.count = a225_registers_count; } list.registers = ®s; list.count = 1; /* Master set of (non debug) registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain, kgsl_snapshot_dump_regs, &list); /* CP_STATE_DEBUG indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_STATE_DEBUG_INDEX, REG_CP_STATE_DEBUG_DATA, 0x0, 0x14); /* CP_ME indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_ME_CNTL, REG_CP_ME_STATUS, 64, 44); /* * Need to temporarily turn off clock gating for the debug bus to * work */ adreno_regread(device, REG_RBBM_PM_OVERRIDE2, &pmoverride); adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, 0xFF); /* SX debug registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a2xx_snapshot_sxdebug, NULL); /* SU debug indexed registers (only for < 470) */ if (!adreno_is_a22x(adreno_dev)) snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_PA_SU_DEBUG_CNTL, REG_PA_SU_DEBUG_DATA, 0, 0x1B); /* CP debug registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a2xx_snapshot_cpdebug, NULL); /* MH debug indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, MH_DEBUG_CTRL, MH_DEBUG_DATA, 0x0, 0x40); /* Leia only register sets */ if (adreno_is_a22x(adreno_dev)) { /* RB DEBUG indexed regisers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_RB_DEBUG_CNTL, REG_RB_DEBUG_DATA, 0, 8); /* RB DEBUG indexed registers bank 2 */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_RB_DEBUG_CNTL, REG_RB_DEBUG_DATA + 0x1000, 0, 8); /* PC_DEBUG indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_PC_DEBUG_CNTL, REG_PC_DEBUG_DATA, 0, 8); /* GRAS_DEBUG indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_GRAS_DEBUG_CNTL, REG_GRAS_DEBUG_DATA, 0, 4); /* MIU debug registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a2xx_snapshot_miudebug, NULL); /* SQ DEBUG debug registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a2xx_snapshot_sqdebug, NULL); /* * Reading SQ THREAD causes bad things to happen on a running * system, so only read it if the GPU is already hung */ if (hang) { /* SQ THREAD debug registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a2xx_snapshot_sqthreaddebug, NULL); } } /* Reset the clock gating */ adreno_regwrite(device, REG_RBBM_PM_OVERRIDE2, pmoverride); return snapshot; }
void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot, int *remain, int hang) { struct kgsl_device *device = &adreno_dev->dev; struct kgsl_snapshot_registers_list list; struct kgsl_snapshot_registers regs[2]; regs[0].regs = (unsigned int *) a3xx_registers; regs[0].count = a3xx_registers_count; list.registers = regs; list.count = 1; /* For A330, append the additional list of new registers to grab */ if (adreno_is_a330(adreno_dev)) { regs[1].regs = (unsigned int *) a330_registers; regs[1].count = a330_registers_count; list.count++; } /* Master set of (non debug) registers */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, remain, kgsl_snapshot_dump_regs, &list); /* CP_STATE_DEBUG indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_STATE_DEBUG_INDEX, REG_CP_STATE_DEBUG_DATA, 0x0, 0x14); /* CP_ME indexed registers */ snapshot = kgsl_snapshot_indexed_registers(device, snapshot, remain, REG_CP_ME_CNTL, REG_CP_ME_STATUS, 64, 44); /* Disable Clock gating temporarily for the debug bus to work */ adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00); /* VPC memory */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_vpc_memory, NULL); /* CP MEQ */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_meq, NULL); /* Shader working/shadow memory */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_shader_memory, NULL); /* CP PFP and PM4 */ /* Reading these will hang the GPU if it isn't already hung */ if (hang) { snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pfp_ram, NULL); snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_pm4_ram, NULL); } /* CP ROQ */ snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a3xx_snapshot_cp_roq, NULL); if (adreno_is_a330(adreno_dev)) { snapshot = kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain, a330_snapshot_cp_merciu, NULL); } snapshot = a3xx_snapshot_debugbus(device, snapshot, remain); /* Enable Clock gating */ adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, A3XX_RBBM_CLOCK_CTL_DEFAULT); return snapshot; }