static int set_clock_info(struct ctrl_cmd *cmd, void *data)
{
struct gsm_bts_trx *trx = cmd->node;
struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
struct msgb *msg = sysp_msgb_alloc();
SuperFemto_Prim_t *sysp = msgb_sysprim(msg);
struct ctrl_cmd_def *cd;
/* geneate a deferred control command */
cd = ctrl_cmd_def_make(fl1h, cmd, NULL, 10);
/* Set GPS/PPS as reference */
sysp->id = SuperFemto_PrimId_RfClockSetupReq;
sysp->u.rfClockSetupReq.rfTrx.iClkCor = fl1h->clk_cal; /* !!! use get_clk_cal */
sysp->u.rfClockSetupReq.rfTrx.clkSrc = fl1h->clk_src;
sysp->u.rfClockSetupReq.rfTrxClkCal.clkSrc = SuperFemto_ClkSrcId_GpsPps;
l1if_req_compl(fl1h, msg, clock_setup_cb, NULL);
/* Reset the error counters */
msg = sysp_msgb_alloc();
sysp = msgb_sysprim(msg);
sysp->id = SuperFemto_PrimId_RfClockInfoReq;
sysp->u.rfClockInfoReq.u8RstClkCal = 1;
l1if_req_compl(fl1h, msg, ctrl_set_clkinfo_cb, cd);
return CTRL_CMD_HANDLED;
}
/* Chapter 12.1 */
int octphy_hw_get_pcb_info(struct octphy_hdl *fl1h)
{
struct msgb *msg = l1p_msgb_alloc();
tOCTVC1_HW_MSG_PCB_INFO_CMD *pic;
pic = (tOCTVC1_HW_MSG_PCB_INFO_CMD *) msgb_put(msg, sizeof(*pic));
l1if_fill_msg_hdr(&pic->Header, msg, fl1h, cOCTVC1_MSG_TYPE_COMMAND,
cOCTVC1_HW_MSG_PCB_INFO_CID);
mOCTVC1_HW_MSG_PCB_INFO_CMD_SWAP(pic);
return l1if_req_compl(fl1h, msg, get_pcb_info_compl_cb, NULL);
}
/* Chapter 12.16 */
int octphy_hw_get_clock_sync_stats(struct octphy_hdl *fl1h)
{
struct msgb *msg = l1p_msgb_alloc();
tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD *csc;
csc = (tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD *)
msgb_put(msg, sizeof(*csc));
l1if_fill_msg_hdr(&csc->Header, msg, fl1h, cOCTVC1_MSG_TYPE_COMMAND,
cOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CID);
mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD_SWAP(csc);
return l1if_req_compl(fl1h, msg, get_clock_sync_stats_cb, NULL);
}
/* Chapter 12.9 */
int octphy_hw_get_rf_port_info(struct octphy_hdl *fl1h, uint32_t index)
{
struct msgb *msg = l1p_msgb_alloc();
tOCTVC1_HW_MSG_RF_PORT_INFO_CMD *pic;
pic = (tOCTVC1_HW_MSG_RF_PORT_INFO_CMD *) msgb_put(msg, sizeof(*pic));
l1if_fill_msg_hdr(&pic->Header, msg, fl1h, cOCTVC1_MSG_TYPE_COMMAND,
cOCTVC1_HW_MSG_RF_PORT_INFO_CID);
pic->ulPortIndex = index;
mOCTVC1_HW_MSG_RF_PORT_INFO_CMD_SWAP(pic);
return l1if_req_compl(fl1h, msg, rf_port_info_compl_cb, NULL);
}
static int get_clock_info(struct ctrl_cmd *cmd, void *data)
{
struct gsm_bts_trx *trx = cmd->node;
struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
struct msgb *msg = sysp_msgb_alloc();
SuperFemto_Prim_t *sysp = msgb_sysprim(msg);
struct ctrl_cmd_def *cd;
/* geneate a deferred control command */
cd = ctrl_cmd_def_make(fl1h, cmd, NULL, 10);
sysp->id = SuperFemto_PrimId_RfClockInfoReq;
sysp->u.rfClockInfoReq.u8RstClkCal = 0;
return l1if_req_compl(fl1h, msg, ctrl_clkinfo_cb, cd);
}
/* Chapter 12.10 */
int octphy_hw_get_rf_port_stats(struct octphy_hdl *fl1h, uint32_t index)
{
struct msgb *msg = l1p_msgb_alloc();
tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *psc;
psc = (tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *) msgb_put(msg, sizeof(*psc));
l1if_fill_msg_hdr(&psc->Header, msg, fl1h, cOCTVC1_MSG_TYPE_COMMAND,
cOCTVC1_HW_MSG_RF_PORT_STATS_CID);
psc->ulPortIndex = index;
psc->ulResetStatsFlag = cOCT_FALSE;
mOCTVC1_HW_MSG_RF_PORT_STATS_CMD_SWAP(psc);
return l1if_req_compl(fl1h, msg, rf_port_stats_compl_cb, NULL);
}
/* Chapter 12.14 */
int octphy_hw_get_rf_ant_tx_config(struct octphy_hdl *fl1h, uint32_t port_idx,
uint32_t ant_idx)
{
struct msgb *msg = l1p_msgb_alloc();
tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *psc;
psc = (tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)
msgb_put(msg, sizeof(*psc));
l1if_fill_msg_hdr(&psc->Header, msg, fl1h, cOCTVC1_MSG_TYPE_COMMAND,
cOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CID);
psc->ulPortIndex = port_idx;
psc->ulAntennaIndex = ant_idx;
mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD_SWAP(psc);
return l1if_req_compl(fl1h, msg, rf_ant_tx_compl_cb, NULL);
}
static int set_clock_corr(struct ctrl_cmd *cmd, void *data)
{
struct gsm_bts_trx *trx = cmd->node;
struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
struct msgb *msg = sysp_msgb_alloc();
SuperFemto_Prim_t *sysp = msgb_sysprim(msg);
struct ctrl_cmd_def *cd;
fl1h->clk_cal = atoi(cmd->value);
/* geneate a deferred control command */
cd = ctrl_cmd_def_make(fl1h, cmd, NULL, 10);
sysp->id = SuperFemto_PrimId_RfClockSetupReq;
sysp->u.rfClockSetupReq.rfTrx.iClkCor = fl1h->clk_cal;
sysp->u.rfClockSetupReq.rfTrx.clkSrc = fl1h->clk_src;
sysp->u.rfClockSetupReq.rfTrxClkCal.clkSrc = SuperFemto_ClkSrcId_GpsPps;
l1if_req_compl(fl1h, msg, ctrl_set_clkcorr_cb, cd);
return CTRL_CMD_HANDLED;
}
static int get_clock_corr(struct ctrl_cmd *cmd, void *data)
{
struct gsm_bts_trx *trx = cmd->node;
struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
struct msgb *msg = sysp_msgb_alloc();
SuperFemto_Prim_t *sysp = msgb_sysprim(msg);
struct ctrl_cmd_def *cd;
/* we could theoretically simply respond with a cached value, but I
* prefer to to ask the actual L1 about the currently used value to
* avoid any mistakes */
/* geneate a deferred control command */
cd = ctrl_cmd_def_make(fl1h, cmd, NULL, 10);
sysp->id = SuperFemto_PrimId_RfClockInfoReq;
sysp->u.rfClockInfoReq.u8RstClkCal = 0;
l1if_req_compl(fl1h, msg, ctrl_get_clkcorr_cb, cd);
return CTRL_CMD_HANDLED;
}
