static void l2x0pmu_stop(void) { unsigned long flags; u32 val; raw_spin_lock_irqsave(&l2x0pmu_hw_events.pmu_lock, flags); val = l2x0pmu_read_ctrl(); val &= ~L2X0_EVENT_CNT_ENABLE_MASK; l2x0pmu_write_ctrl(val); if (!rev1) l2x0_disable_counter_interrupt(); raw_spin_unlock_irqrestore(&l2x0pmu_hw_events.pmu_lock, flags); }
static void l2x0pmu_stop(void) { unsigned long flags; u32 val; raw_spin_lock_irqsave(&l2x0pmu_hw_events.pmu_lock, flags); val = l2x0pmu_read_ctrl(); val &= ~L2X0_EVENT_CNT_ENABLE_MASK; l2x0pmu_write_ctrl(val); /* * TODO: Disable counter interrupt, * once we know it works on this chip. */ raw_spin_unlock_irqrestore(&l2x0pmu_hw_events.pmu_lock, flags); }