int cfb_init(struct CFB_STATE *state,
struct BLOCK_STATE *cipher_state,
const void *iv, size_t iv_len,
int dir,
const void *params)
{
int err;
struct BLOCK_MODE_LIMITS limits;
struct BLOCK_LIMITS block_lims;
if ((err = cfb_limits(cipher_state->primitive, &limits)))
return err;
if ((err = block_limits(cipher_state->primitive, &block_lims)))
return err;
state->block_size = block_lims.block_size;
if (!limit_check(iv_len, limits.iv_min, limits.iv_max, limits.iv_mul))
return ORDO_ARG;
state->direction = dir;
memset(state->iv, 0x00, state->block_size);
memcpy(state->iv, iv, iv_len);
block_forward(cipher_state, state->iv);
state->remaining = state->block_size;
return ORDO_SUCCESS;
}
int aes_init(struct AES_STATE *state,
const void *key, size_t key_len,
const struct AES_PARAMS *params)
{
if (!limit_check(key_len, bits(128), bits(256), bits(64)))
return ORDO_KEY_LEN;
if (params)
{
if (params->rounds == 0) return ORDO_ARG;
if (params->rounds > 20) return ORDO_ARG;
state->rounds = params->rounds;
}
else
{
/* Set the default round numbers. */
if (key_len == 16) state->rounds = 10;
else if (key_len == 24) state->rounds = 12;
else if (key_len == 32) state->rounds = 14;
}
ExpandKey((uint8_t *)key, state->key, key_len / 4, state->rounds);
return ORDO_SUCCESS;
}
int threefish256_init(struct THREEFISH256_STATE *state,
const void *key, size_t key_len,
const struct THREEFISH256_PARAMS *params)
{
uint64_t data[4];
if (!limit_check(key_len, bits(256), bits(256), 1))
return ORDO_KEY_LEN;
memcpy(data, key, sizeof(data));
threefish256_key_schedule(data, (params == 0) ? 0 : params->tweak,
state->subkey);
return ORDO_SUCCESS;
}
int test_limit_check(void)
{
ASSERT_EQ(limit_check(6, 8, 16, 4), 0);
ASSERT_EQ(limit_check(20, 8, 16, 4), 0);
ASSERT_EQ(limit_check(9, 8, 16, 4), 0);
ASSERT_EQ(limit_check(10, 13, 13, 1), 0);
ASSERT_EQ(limit_check(19, 13, 13, 1), 0);
ASSERT_EQ(limit_check(13, 13, 13, 1), 1);
ASSERT_EQ(limit_check(15, 20, 40, 1), 0);
ASSERT_EQ(limit_check(45, 20, 40, 1), 0);
ASSERT_EQ(limit_check(25, 20, 40, 1), 1);
ASSERT_EQ(limit_check(31, 20, 40, 1), 1);
ASSERT_EQ(limit_check(15, 20, 40, 2), 0);
ASSERT_EQ(limit_check(45, 20, 40, 2), 0);
ASSERT_EQ(limit_check(25, 20, 40, 2), 0);
ASSERT_EQ(limit_check(31, 20, 40, 2), 0);
ASSERT_EQ(limit_check(0, 0, 6, 3), 1);
ASSERT_EQ(limit_check(2, 0, 6, 3), 0);
ASSERT_EQ(limit_check(4, 0, 6, 3), 0);
ASSERT_EQ(limit_check(6, 0, 6, 3), 1);
ASSERT_EQ(limit_check(8, 0, 6, 3), 0);
return 1;
}
void step_state()
{
static int count = 0;
static int max_current_error_count = 0;
static int max_amp_temperature_count = 0;
if (limit_check(ABS(get_max_current_ma()), max_current_ma,
&max_current_error_count, max_current_error_count_max) )
dsp = DSP_ERROR;
if (limit_check(get_temperature_cC(ADC_AMP_TEMP), max_amp_temperature_cC,
&max_amp_temperature_count, max_amp_temperature_count_max) )
dsp = DSP_ERROR;
if (count<1000) {
count++;
dsp = DSP_STARTUP;
} else if (dsp != DSP_ERROR) { // latch in the error mode
switch (ec_cmd.command[0].mode) {
case 0:
dsp = DSP_OFF;
break;
case 1:
dsp = DSP_PWM;
break;
case 2:
dsp = DSP_OFF;
break;
case 3:
dsp = DSP_CURRENT;
break;
case 4:
default:
dsp = DSP_BRAKE;
break;
}
}
switch (dsp) {
case DSP_OFF:
set_current_command_ma(0);
set_pwm_desired(0);
set_bldc_open();
break;
case DSP_STARTUP:
set_current_command_ma(0);
set_pwm_desired(0);
set_bldc_open();
set_adc_zeros();
break;
case DSP_PWM:
set_current_command_ma(0);
set_pwm_desired(ec_cmd.command[0].pwm_desired);
set_bldc_commutation();
break;
case DSP_CURRENT:
set_current_command_ma(ec_cmd.command[0].current_desired);
set_pwm_desired(0);
set_bldc_commutation();
break;
case DSP_BRAKE:
set_current_command_ma(0);
set_pwm_desired(0);
set_bldc_brake();
break;
case DSP_ERROR:
default:
set_current_command_ma(0);
set_pwm_desired(0);
set_bldc_open();
break;
}
}
