void lpc43_clockconfig(void)
{
/* Configure the crystal input to PLL1 */
lpc43_xtalconfig();
#ifndef PLL_RAMP
/* Configure PLL1 */
lpc43_pll1config(PLL_CONTROLS);
/* Enable PLL1 */
lpc43_pll1enable();
/* Set up PLL1 output as the M4 clock */
lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
#else
/* Drive the M4 clock from the XTAL until the PLL is configured */
lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
/* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
lpc43_pll1config(INIT_PLL_CONTROLS);
/* Enable PLL1 */
lpc43_pll1enable();
/* Delay around 10 milliseconds */
up_mdelay(XTAL_DELAY);
/* Configure the intermediate, ramp-up configuration for PLL1 */
lpc43_pll1config(RAMP_PLL_CONTROLS);
/* Set up PLL1 output as the M4 clock */
lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
/* Delay around 10 milliseconds */
up_mdelay(XTAL_DELAY);
/* Go to the final, full-speed PLL1 configuration */
lpc43_pll1config(PLL_CONTROLS);
#endif
}
void lpc43_clockconfig(void)
{
/* Configure the crystal input to PLL1 */
lpc43_xtalconfig();
#ifndef PLL_RAMP
/* Configure PLL1 */
lpc43_pll1config(PLL_CONTROLS);
/* Enable PLL1 */
lpc43_pll1enable();
/* Set up PLL1 output as the M4 clock */
lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
#else
/* Drive the M4 clock from the XTAL until the PLL is configured */
lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
/* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
lpc43_pll1config(INIT_PLL_CONTROLS);
/* Enable PLL1 */
lpc43_pll1enable();
/* Delay around 10 milliseconds */
up_mdelay(XTAL_DELAY);
/* Configure the intermediate, ramp-up configuration for PLL1 */
lpc43_pll1config(RAMP_PLL_CONTROLS);
/* Set up PLL1 output as the M4 clock */
lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
/* Delay around 10 milliseconds */
up_mdelay(XTAL_DELAY);
/* Go to the final, full-speed PLL1 configuration */
lpc43_pll1config(PLL_CONTROLS);
#endif
/* Configure idivs */
#if defined(BOARD_IDIVA_DIVIDER) && defined(BOARD_IDIVA_CLKSRC)
lpc43_idiva();
#endif
#if defined(BOARD_IDIVB_DIVIDER) && defined(BOARD_IDIVB_CLKSRC)
lpc43_idivb();
#endif
#if defined(BOARD_IDIVC_DIVIDER) && defined(BOARD_IDIVC_CLKSRC)
lpc43_idivc();
#endif
#if defined(BOARD_IDIVD_DIVIDER) && defined(BOARD_IDIVD_CLKSRC)
lpc43_idivd();
#endif
#if defined(BOARD_IDIVE_DIVIDER) && defined(BOARD_IDIVE_CLKSRC)
lpc43_idive();
#endif
/* Configure abpXs */
#if defined(BOARD_ABP1_CLKSRC)
lpc43_abp1();
#endif
#if defined(BOARD_ABP3_CLKSRC)
lpc43_abp3();
#endif
}