/* Return whether current thread is stopped due to a watchpoint. */
static int
arm_stopped_by_watchpoint (void)
{
struct lwp_info *lwp = get_thread_lwp (current_thread);
siginfo_t siginfo;
/* We must be able to set hardware watchpoints. */
if (arm_linux_get_hw_watchpoint_count () == 0)
return 0;
/* Retrieve siginfo. */
errno = 0;
ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo);
if (errno != 0)
return 0;
/* This must be a hardware breakpoint. */
if (siginfo.si_signo != SIGTRAP
|| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
return 0;
/* If we are in a positive slot then we're looking at a breakpoint and not
a watchpoint. */
if (siginfo.si_errno >= 0)
return 0;
/* Cache stopped data address for use by arm_stopped_data_address. */
lwp->arch_private->stopped_data_address
= (CORE_ADDR) (uintptr_t) siginfo.si_addr;
return 1;
}
static void
aarch64_arch_setup (void)
{
current_process ()->tdesc = aarch64_linux_read_description ();
aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
}
static CORE_ADDR
aarch64_stopped_data_address (void)
{
siginfo_t siginfo;
int pid, i;
struct aarch64_debug_reg_state *state;
pid = lwpid_of (current_thread);
/* Get the siginfo. */
if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
return (CORE_ADDR) 0;
/* Need to be a hardware breakpoint/watchpoint trap. */
if (siginfo.si_signo != SIGTRAP
|| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
return (CORE_ADDR) 0;
/* Check if the address matches any watched address. */
state = aarch64_get_debug_reg_state (pid_of (current_thread));
for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
{
const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
const CORE_ADDR addr_watch = state->dr_addr_wp[i];
if (state->dr_ref_count_wp[i]
&& DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
&& addr_trap >= addr_watch
&& addr_trap < addr_watch + len)
return addr_trap;
}
return (CORE_ADDR) 0;
}
static void
aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
{
struct thread_info *thread = get_lwp_thread (lwp);
ptid_t ptid = ptid_of (thread);
struct arch_lwp_info *info = lwp->arch_private;
if (DR_HAS_CHANGED (info->dr_changed_bp)
|| DR_HAS_CHANGED (info->dr_changed_wp))
{
int tid = ptid_get_lwp (ptid);
struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
struct aarch64_debug_reg_state *state
= &proc->priv->arch_private->debug_reg_state;
if (show_debug_regs)
fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
/* Watchpoints. */
if (DR_HAS_CHANGED (info->dr_changed_wp))
{
aarch64_linux_set_debug_regs (state, tid, 1);
DR_CLEAR_CHANGED (info->dr_changed_wp);
}
/* Breakpoints. */
if (DR_HAS_CHANGED (info->dr_changed_bp))
{
aarch64_linux_set_debug_regs (state, tid, 0);
DR_CLEAR_CHANGED (info->dr_changed_bp);
}
}
}
static void
mips_arch_setup (void)
{
static void (*init_registers) (void);
gdb_assert (current_inferior);
if (init_registers == NULL)
{
int pid = lwpid_of (get_thread_lwp (current_inferior));
ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
switch (errno)
{
case 0:
the_low_target.num_regs = mips_dsp_num_regs;
the_low_target.regmap = mips_dsp_regmap;
the_low_target.regset_bitmap = mips_dsp_regset_bitmap;
init_registers = init_registers_mips_dsp_linux;
break;
case EIO:
the_low_target.num_regs = mips_num_regs;
the_low_target.regmap = mips_regmap;
the_low_target.regset_bitmap = NULL;
init_registers = init_registers_mips_linux;
break;
default:
perror_with_name ("ptrace");
break;
}
}
init_registers ();
}
static void
arm_arch_setup (void)
{
arm_hwcap = 0;
if (arm_get_hwcap (&arm_hwcap) == 0)
{
init_registers_arm ();
return;
}
/* gdbserver assumes that only one of VFP or IWMMXT is available, which may
not be true. In that case, gdbserver fails at run-time with "Unknown
register d0 requested". For now, pretend IWMMXT is missing when both are
available. */
if ((arm_hwcap & HWCAP_VFP) && (arm_hwcap & HWCAP_IWMMXT))
arm_hwcap &= ~HWCAP_IWMMXT;
if (arm_hwcap & HWCAP_IWMMXT)
{
init_registers_arm_with_iwmmxt ();
return;
}
if (arm_hwcap & HWCAP_VFP)
{
int pid;
char *buf;
/* NEON implies either no VFP, or VFPv3-D32. We only support
it with VFP. */
if (arm_hwcap & HWCAP_NEON)
init_registers_arm_with_neon ();
else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
init_registers_arm_with_vfpv3 ();
else
init_registers_arm_with_vfpv2 ();
/* Now make sure that the kernel supports reading these
registers. Support was added in 2.6.30. */
pid = lwpid_of (get_thread_lwp (current_inferior));
errno = 0;
buf = malloc (32 * 8 + 4);
if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
&& errno == EIO)
{
arm_hwcap = 0;
init_registers_arm ();
}
free (buf);
return;
}
/* The default configuration uses legacy FPA registers, probably
simulated. */
init_registers_arm ();
}
static void
aarch64_arch_setup (void)
{
int pid;
struct iovec iov;
struct user_hwdebug_state dreg_state;
current_process ()->tdesc = tdesc_aarch64;
pid = lwpid_of (current_thread);
iov.iov_base = &dreg_state;
iov.iov_len = sizeof (dreg_state);
/* Get hardware watchpoint register info. */
if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
{
aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
{
warning ("Unexpected number of hardware watchpoint registers reported"
" by ptrace, got %d, expected %d.",
aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
}
}
else
{
warning ("Unable to determine the number of hardware watchpoints"
" available.");
aarch64_num_wp_regs = 0;
}
/* Get hardware breakpoint register info. */
if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
{
aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
{
warning ("Unexpected number of hardware breakpoint registers reported"
" by ptrace, got %d, expected %d.",
aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
}
}
else
{
warning ("Unable to determine the number of hardware breakpoints"
" available.");
aarch64_num_bp_regs = 0;
}
}
/* Called when resuming a thread.
If the debug regs have changed, update the thread's copies. */
static void
arm_prepare_to_resume (struct lwp_info *lwp)
{
struct thread_info *thread = get_lwp_thread (lwp);
int pid = lwpid_of (thread);
struct process_info *proc = find_process_pid (pid_of (thread));
struct arch_process_info *proc_info = proc->priv->arch_private;
struct arch_lwp_info *lwp_info = lwp->arch_private;
int i;
for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++)
if (lwp_info->bpts_changed[i])
{
errno = 0;
if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control))
if (ptrace (PTRACE_SETHBPREGS, pid,
(PTRACE_TYPE_ARG3) ((i << 1) + 1),
&proc_info->bpts[i].address) < 0)
perror_with_name ("Unexpected error setting breakpoint address");
if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control))
if (ptrace (PTRACE_SETHBPREGS, pid,
(PTRACE_TYPE_ARG3) ((i << 1) + 2),
&proc_info->bpts[i].control) < 0)
perror_with_name ("Unexpected error setting breakpoint");
lwp_info->bpts_changed[i] = 0;
}
for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++)
if (lwp_info->wpts_changed[i])
{
errno = 0;
if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control))
if (ptrace (PTRACE_SETHBPREGS, pid,
(PTRACE_TYPE_ARG3) -((i << 1) + 1),
&proc_info->wpts[i].address) < 0)
perror_with_name ("Unexpected error setting watchpoint address");
if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control))
if (ptrace (PTRACE_SETHBPREGS, pid,
(PTRACE_TYPE_ARG3) -((i << 1) + 2),
&proc_info->wpts[i].control) < 0)
perror_with_name ("Unexpected error setting watchpoint");
lwp_info->wpts_changed[i] = 0;
}
}
static void
arm_arch_setup (void)
{
arm_hwcap = 0;
if (arm_get_hwcap (&arm_hwcap) == 0)
{
init_registers_arm ();
return;
}
if (arm_hwcap & HWCAP_IWMMXT)
{
init_registers_arm_with_iwmmxt ();
return;
}
if (arm_hwcap & HWCAP_VFP)
{
int pid;
char *buf;
/* NEON implies either no VFP, or VFPv3-D32. We only support
it with VFP. */
if (arm_hwcap & HWCAP_NEON)
init_registers_arm_with_neon ();
else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
init_registers_arm_with_vfpv3 ();
else
init_registers_arm_with_vfpv2 ();
/* Now make sure that the kernel supports reading these
registers. Support was added in 2.6.30. */
pid = lwpid_of (get_thread_lwp (current_inferior));
errno = 0;
buf = malloc (32 * 8 + 4);
if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
&& errno == EIO)
{
arm_hwcap = 0;
init_registers_arm ();
}
free (buf);
return;
}
/* The default configuration uses legacy FPA registers, probably
simulated. */
init_registers_arm ();
}
static const struct target_desc *
arm_read_description (void)
{
int pid = lwpid_of (current_thread);
/* Query hardware watchpoint/breakpoint capabilities. */
arm_linux_init_hwbp_cap (pid);
arm_hwcap = 0;
if (arm_get_hwcap (&arm_hwcap) == 0)
return tdesc_arm;
if (arm_hwcap & HWCAP_IWMMXT)
return tdesc_arm_with_iwmmxt;
if (arm_hwcap & HWCAP_VFP)
{
const struct target_desc *result;
char *buf;
/* NEON implies either no VFP, or VFPv3-D32. We only support
it with VFP. */
if (arm_hwcap & HWCAP_NEON)
result = tdesc_arm_with_neon;
else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
result = tdesc_arm_with_vfpv3;
else
result = tdesc_arm_with_vfpv2;
/* Now make sure that the kernel supports reading these
registers. Support was added in 2.6.30. */
errno = 0;
buf = xmalloc (32 * 8 + 4);
if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
&& errno == EIO)
{
arm_hwcap = 0;
result = tdesc_arm;
}
free (buf);
return result;
}
/* The default configuration uses legacy FPA registers, probably
simulated. */
return tdesc_arm;
}
static const struct target_desc *
aarch64_linux_read_description (void)
{
unsigned int machine;
int is_elf64;
int tid;
tid = lwpid_of (current_thread);
is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
if (is_elf64)
return tdesc_aarch64;
else
return tdesc_arm_with_neon;
}
static void
arm_arch_setup (void)
{
int tid = lwpid_of (current_thread);
int gpregs[18];
struct iovec iov;
current_process ()->tdesc = arm_read_description ();
iov.iov_base = gpregs;
iov.iov_len = sizeof (gpregs);
/* Check if PTRACE_GETREGSET works. */
if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0)
have_ptrace_getregset = 1;
else
have_ptrace_getregset = 0;
}
static int
debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr)
{
struct thread_info *thread = (struct thread_info *) entry;
struct lwp_info *lwp = get_thread_lwp (thread);
struct aarch64_dr_update_callback_param *param_p
= (struct aarch64_dr_update_callback_param *) ptr;
int pid = param_p->pid;
int idx = param_p->idx;
int is_watchpoint = param_p->is_watchpoint;
struct arch_lwp_info *info = lwp->arch_private;
dr_changed_t *dr_changed_ptr;
dr_changed_t dr_changed;
if (show_debug_regs)
{
fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
"dr_changed_wp=0x%llx\n",
pid, lwpid_of (thread), info->dr_changed_bp,
info->dr_changed_wp);
}
dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
: &info->dr_changed_bp;
dr_changed = *dr_changed_ptr;
/* Only update the threads of this process. */
if (pid_of (thread) == pid)
{
gdb_assert (idx >= 0
&& (idx <= (is_watchpoint ? aarch64_num_wp_regs
: aarch64_num_bp_regs)));
/* The following assertion is not right, as there can be changes
that have not been made to the hardware debug registers
before new changes overwrite the old ones. This can happen,
for instance, when the breakpoint/watchpoint hit one of the
threads and the user enters continue; then what happens is:
1) all breakpoints/watchpoints are removed for all threads;
2) a single step is carried out for the thread that was hit;
3) all of the points are inserted again for all threads;
4) all threads are resumed.
The 2nd step will only affect the one thread in which the
bp/wp was hit, which means only that one thread is resumed;
remember that the actual updating only happen in
aarch64_linux_prepare_to_resume, so other threads remain
stopped during the removal and insertion of bp/wp. Therefore
for those threads, the change of insertion of the bp/wp
overwrites that of the earlier removals. (The situation may
be different when bp/wp is steppable, or in the non-stop
mode.) */
/* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
/* The actual update is done later just before resuming the lwp,
we just mark that one register pair needs updating. */
DR_MARK_N_CHANGED (dr_changed, idx);
*dr_changed_ptr = dr_changed;
/* If the lwp isn't stopped, force it to momentarily pause, so
we can update its debug registers. */
if (!lwp->stopped)
linux_stop_lwp (lwp);
}
if (show_debug_regs)
{
fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
"dr_changed_wp=0x%llx\n",
pid, lwpid_of (thread), info->dr_changed_bp,
info->dr_changed_wp);
}
return 0;
}
