static int sec_init(struct eth_device *dev, bd_t *bis) { int i; volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; scc_enet_t *pram_ptr; uint dpaddr; uchar ea[6]; rxIdx = 0; txIdx = 0; /* * Assign static pointer to BD area. * Avoid exhausting DPRAM, which would cause a panic. */ if (rtx == NULL) { dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; } /* 24.21 - (1-3): ioports have been set up already */ /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ immr->im_cpmux.cmx_uar = 0; immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | CONFIG_SYS_CMXSCR_VALUE); /* 24.21 (6) write RBASE and TBASE to parameter RAM */ pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, CPM_CR_ENET_SBLOCK, 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; /* 24.21 - (8-18): Set up parameter RAM */ pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ eth_getenv_enetaddr("ethaddr", ea); pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ /* 24.21 - (19): Initialize RxBD */ for (i = 0; i < PKTBUFSRX; i++) { rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx->rxbd[i].cbd_datlen = 0; /* Reset */ rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; } rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; /* 24.21 - (20): Initialize TxBD */ for (i = 0; i < TX_BUF_CNT; i++) { rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); rtx->txbd[i].cbd_datlen = 0; /* Reset */ rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; } rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; /* 24.21 - (21): Write 0xffff to SCCE */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); /* 24.21 - (23): we don't use ethernet interrupts */ /* 24.21 - (24): Clear GSMR_H to enable normal operations */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; /* 24.21 - (25): Clear GSMR_L to enable normal operations */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); /* 24.21 - (26): Initialize DSR */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; /* 24.21 - (27): Initialize PSMR2 * * Settings: * CRC = 32-Bit CCITT * NIB = Begin searching for SFD 22 bits after RENA * FDE = Full Duplex Enable * BRO = Reject broadcast packets * PROMISCOUS = Catch all packets regardless of dest. MAC adress */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | #if defined(CONFIG_SCC_ENET_FULL_DUPLEX) SCC_PSMR_FDE | #endif #if defined(CONFIG_SCC_ENET_NO_BROADCAST) SCC_PSMR_BRO | #endif #if defined(CONFIG_SCC_ENET_PROMISCOUS) SCC_PSMR_PRO | #endif 0; /* 24.21 - (28): Write to GSMR_L to enable SCC */ immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); return 0; }
static int mpc8260_smc_serial_init(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cpm8260_t *cp = &(im->im_cpm); uint dpaddr; volatile serialbuffer_t *rtx; /* initialize pointers to SMC */ sp = (smc_t *) &(im->im_smc[SMC_INDEX]); *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC; up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; /* Disable transmitter/receiver. */ sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ /* Allocate space for two buffer descriptors in the DP ram. * damm: allocating space after the two buffers for rx/tx data */ /* allocate size of struct serialbuffer with bd rx/tx, * buffer rx/tx and rx index */ dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16); rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr]; /* Set the physical address of the host memory buffers in * the buffer descriptors. */ rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; rtx->rxbd.cbd_sc = 0; rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; rtx->txbd.cbd_sc = 0; /* Set up the uart parameters in the parameter ram. */ up->smc_rbase = dpaddr; up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = CPMFCR_EB; up->smc_tfcr = CPMFCR_EB; up->smc_brklen = 0; up->smc_brkec = 0; up->smc_brkcr = 0; /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. */ sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; /* Mask all interrupts and remove anything pending. */ sp->smc_smcm = 0; sp->smc_smce = 0xff; /* put the SMC channel into NMSI (non multiplexd serial interface) * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). */ im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; /* Set up the baud rate generator. */ serial_setbrg (); /* Make the first buffer the only buffer. */ rtx->txbd.cbd_sc |= BD_SC_WRAP; rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; /* single/multi character receive. */ up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; up->smc_maxidl = CONFIG_SYS_MAXIDLE; rtx->rxindex = 0; /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; /* Enable transmitter/receiver. */ sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; return (0); }
void kgdb_serial_init (void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; volatile cpm8260_t *cp = &(im->im_cpm); uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; char *s, *e; if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { ulong rate = simple_strtoul(s, &e, 10); if (e > s && *e == '\0') speed = rate; } /* initialize pointers to SMC */ sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]); *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC; up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; /* Disable transmitter/receiver. */ sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ /* Allocate space for two buffer descriptors in the DP ram. * damm: allocating space after the two buffers for rx/tx data */ dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); /* Set the physical address of the host memory buffers in * the buffer descriptors. */ rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = 0; tbdf = rbdf + 1; tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; tbdf->cbd_sc = 0; /* Set up the uart parameters in the parameter ram. */ up->smc_rbase = dpaddr; up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = CPMFCR_EB; up->smc_tfcr = CPMFCR_EB; up->smc_brklen = 0; up->smc_brkec = 0; up->smc_brkcr = 0; /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. */ sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; /* Mask all interrupts and remove anything pending. */ sp->smc_smcm = 0; sp->smc_smce = 0xff; /* put the SMC channel into NMSI (non multiplexd serial interface) * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). */ im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; /* Set up the baud rate generator. */ #if defined(CONFIG_KGDB_USE_EXTC) m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); #else m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); #endif /* Make the first buffer the only buffer. */ tbdf->cbd_sc |= BD_SC_WRAP; rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; /* Single character receive. */ up->smc_mrblr = 1; up->smc_maxidl = 0; /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; /* Enable transmitter/receiver. */ sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); }
/* Initialize the CPM Ethernet on SCC. */ int __init scc_enet_init(void) { struct net_device *dev; struct scc_enet_private *cep; int i, j; unsigned char *eap; unsigned long mem_addr; bd_t *bd; volatile cbd_t *bdp; volatile cpm8260_t *cp; volatile scc_t *sccp; volatile scc_enet_t *ep; volatile immap_t *immap; volatile iop8260_t *io; cp = cpmp; /* Get pointer to Communication Processor */ immap = (immap_t *)IMAP_ADDR; /* and to internal registers */ io = &immap->im_ioport; bd = (bd_t *)__res; /* Allocate some private information. */ cep = (struct scc_enet_private *)kmalloc(sizeof(*cep), GFP_KERNEL); if (cep == NULL) return -ENOMEM; __clear_user(cep,sizeof(*cep)); spin_lock_init(&cep->lock); /* Create an Ethernet device instance. */ dev = init_etherdev(0, 0); /* Get pointer to SCC area in parameter RAM. */ ep = (scc_enet_t *)(&immap->im_dprambase[PROFF_ENET]); /* And another to the SCC register area. */ sccp = (volatile scc_t *)(&immap->im_scc[SCC_ENET]); cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */ /* Disable receive and transmit in case someone left it running. */ sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); /* Configure port C and D pins for SCC Ethernet. This * won't work for all SCC possibilities....it will be * board/port specific. */ io->iop_pparc |= (PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK); io->iop_pdirc &= ~(PC_ENET_RENA | PC_ENET_CLSN | PC_ENET_TXCLK | PC_ENET_RXCLK); io->iop_psorc &= ~(PC_ENET_RENA | PC_ENET_TXCLK | PC_ENET_RXCLK); io->iop_psorc |= PC_ENET_CLSN; io->iop_ppard |= (PD_ENET_RXD | PD_ENET_TXD | PD_ENET_TENA); io->iop_pdird |= (PD_ENET_TXD | PD_ENET_TENA); io->iop_pdird &= ~PD_ENET_RXD; io->iop_psord |= PD_ENET_TXD; io->iop_psord &= ~(PD_ENET_RXD | PD_ENET_TENA); /* Configure Serial Interface clock routing. * First, clear all SCC bits to zero, then set the ones we want. */ immap->im_cpmux.cmx_scr &= ~CMX_CLK_MASK; immap->im_cpmux.cmx_scr |= CMX_CLK_ROUTE; /* Allocate space for the buffer descriptors in the DP ram. * These are relative offsets in the DP ram address space. * Initialize base addresses for the buffer descriptors. */ i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8); ep->sen_genscc.scc_rbase = i; cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i]; i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8); ep->sen_genscc.scc_tbase = i; cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i]; cep->dirty_tx = cep->cur_tx = cep->tx_bd_base; cep->cur_rx = cep->rx_bd_base; ep->sen_genscc.scc_rfcr = CPMFCR_GBL | CPMFCR_EB; ep->sen_genscc.scc_tfcr = CPMFCR_GBL | CPMFCR_EB; /* Set maximum bytes per receive buffer. * This appears to be an Ethernet frame size, not the buffer * fragment size. It must be a multiple of four. */ ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE; /* Set CRC preset and mask. */ ep->sen_cpres = 0xffffffff; ep->sen_cmask = 0xdebb20e3; ep->sen_crcec = 0; /* CRC Error counter */ ep->sen_alec = 0; /* alignment error counter */ ep->sen_disfc = 0; /* discard frame counter */ ep->sen_pads = 0x8888; /* Tx short frame pad character */ ep->sen_retlim = 15; /* Retry limit threshold */ ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */ ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */ /* Clear hash tables. */ ep->sen_gaddr1 = 0; ep->sen_gaddr2 = 0; ep->sen_gaddr3 = 0; ep->sen_gaddr4 = 0; ep->sen_iaddr1 = 0; ep->sen_iaddr2 = 0; ep->sen_iaddr3 = 0; ep->sen_iaddr4 = 0; /* Set Ethernet station address. * * This is supplied in the board information structure, so we * copy that into the controller. */ eap = (unsigned char *)&(ep->sen_paddrh); for (i=5; i>=0; i--) *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i]; ep->sen_pper = 0; /* 'cause the book says so */ ep->sen_taddrl = 0; /* temp address (LSB) */ ep->sen_taddrm = 0; ep->sen_taddrh = 0; /* temp address (MSB) */ /* Now allocate the host memory pages and initialize the * buffer descriptors. */ bdp = cep->tx_bd_base; for (i=0; i<TX_RING_SIZE; i++) { /* Initialize the BD for every fragment in the page. */ bdp->cbd_sc = 0; bdp->cbd_bufaddr = 0; bdp++; } /* Set the last buffer to wrap. */ bdp--; bdp->cbd_sc |= BD_SC_WRAP; bdp = cep->rx_bd_base; for (i=0; i<CPM_ENET_RX_PAGES; i++) { /* Allocate a page. */ mem_addr = __get_free_page(GFP_KERNEL); /* Initialize the BD for every fragment in the page. */ for (j=0; j<CPM_ENET_RX_FRPPG; j++) { bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR; bdp->cbd_bufaddr = __pa(mem_addr); mem_addr += CPM_ENET_RX_FRSIZE; bdp++; } } /* Set the last buffer to wrap. */ bdp--; bdp->cbd_sc |= BD_SC_WRAP; /* Let's re-initialize the channel now. We have to do it later * than the manual describes because we have just now finished * the BD initialization. */ cpmp->cp_cpcr = mk_cr_cmd(CPM_ENET_PAGE, CPM_ENET_BLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG); cep->skb_cur = cep->skb_dirty = 0; sccp->scc_scce = 0xffff; /* Clear any pending events */ /* Enable interrupts for transmit error, complete frame * received, and any transmit buffer we have also set the * interrupt flag. */ sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB); /* Install our interrupt handler. */ request_irq(SIU_INT_ENET, scc_enet_interrupt, 0, "enet", dev); /* Set GSMR_H to enable all normal operating modes. * Set GSMR_L to enable Ethernet to MC68160. */ sccp->scc_gsmrh = 0; sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET); /* Set sync/delimiters. */ sccp->scc_dsr = 0xd555; /* Set processing mode. Use Ethernet CRC, catch broadcast, and * start frame search 22 bit times after RENA. */ sccp->scc_pmsr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22); /* It is now OK to enable the Ethernet transmitter. * Unfortunately, there are board implementation differences here. */ io->iop_pparc &= ~(PC_EST8260_ENET_LOOPBACK | PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); io->iop_psorc &= ~(PC_EST8260_ENET_LOOPBACK | PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); io->iop_pdirc |= (PC_EST8260_ENET_LOOPBACK | PC_EST8260_ENET_SQE | PC_EST8260_ENET_NOTFD); io->iop_pdatc &= ~(PC_EST8260_ENET_LOOPBACK | PC_EST8260_ENET_SQE); io->iop_pdatc |= PC_EST8260_ENET_NOTFD; dev->base_addr = (unsigned long)ep; dev->priv = cep; /* The CPM Ethernet specific entries in the device structure. */ dev->open = scc_enet_open; dev->hard_start_xmit = scc_enet_start_xmit; dev->tx_timeout = scc_enet_timeout; dev->watchdog_timeo = TX_TIMEOUT; dev->stop = scc_enet_close; dev->get_stats = scc_enet_get_stats; dev->set_multicast_list = set_multicast_list; /* And last, enable the transmit and receive processing. */ sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); printk("%s: SCC ENET Version 0.1, ", dev->name); for (i=0; i<5; i++) printk("%02x:", dev->dev_addr[i]); printk("%02x\n", dev->dev_addr[5]); return 0; }
/* We also own one page of host buffer space for the allocation of * UART "fifos" and the like. */ uint m8260_cpm_hostalloc(uint size, uint align) { /* the host might not even have RAM yet - just use dual port RAM */ return (m8260_cpm_dpalloc(size, align)); }
int serial_init (void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; volatile cpm8260_t *cp = &(im->im_cpm); uint dpaddr; /* initialize pointers to SCC */ sp = (scc_t *) &(im->im_scc[SCC_INDEX]); up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; /* Disable transmitter/receiver. */ sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); /* put the SCC channel into NMSI (non multiplexd serial interface) * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). */ im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE; /* Set up the baud rate generator. */ serial_setbrg (); /* Allocate space for two buffer descriptors in the DP ram. * damm: allocating space after the two buffers for rx/tx data */ dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); /* Set the physical address of the host memory buffers in * the buffer descriptors. */ rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; tbdf = rbdf + 1; tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; tbdf->cbd_sc = BD_SC_WRAP; /* Set up the uart parameters in the parameter ram. */ up->scc_genscc.scc_rbase = dpaddr; up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); up->scc_genscc.scc_rfcr = CPMFCR_EB; up->scc_genscc.scc_tfcr = CPMFCR_EB; up->scc_genscc.scc_mrblr = 1; up->scc_maxidl = 0; up->scc_brkcr = 1; up->scc_parec = 0; up->scc_frmec = 0; up->scc_nosec = 0; up->scc_brkec = 0; up->scc_uaddr1 = 0; up->scc_uaddr2 = 0; up->scc_toseq = 0; up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; up->scc_rccm = 0xc0ff; /* Mask all interrupts and remove anything pending. */ sp->scc_sccm = 0; sp->scc_scce = 0xffff; /* Set 8 bit FIFO, 16 bit oversampling and UART mode. */ sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ sp->scc_gsmrl = \ SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; /* Set CTS flow control, 1 stop bit, 8 bit character length, * normal async UART mode, no parity */ sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; /* execute the "Init Rx and Tx params" CP command. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; /* Enable transmitter/receiver. */ sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; return (0); }