void * asmlinkage romstage_main(unsigned long bist) { int i; void *romstage_stack_after_car; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - DCACHE_RAM_ROMSTAGE_STACK_SIZE); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; mainboard_romstage_entry(bist); /* Check the stack. */ for (i = 0; i < num_guards; i++) { if (stack_base[i] == stack_guard) continue; printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } /* Get the stack to use after cache-as-ram is torn down. */ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) romstage_stack_after_car = (void*)CONFIG_RAMTOP; else romstage_stack_after_car = setup_stack_and_mtrrs(); return romstage_stack_after_car; }
static void romstage_main(unsigned long bist) { int i; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base; u32 size; /* Size of unallocated CAR. */ size = ALIGN_DOWN(_car_stack_size, 16); size = MIN(size, DCACHE_RAM_ROMSTAGE_STACK_SIZE); if (size < DCACHE_RAM_ROMSTAGE_STACK_SIZE) printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n", size); stack_base = (u32 *) (_car_stack_end - size); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; mainboard_romstage_entry(bist); /* Check the stack. */ for (i = 0; i < num_guards; i++) { if (stack_base[i] == stack_guard) continue; printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } platform_enter_postcar(); }
asmlinkage void *romstage_main(unsigned long bist) { int i; void *romstage_stack_after_car; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); printk(BIOS_DEBUG, "Setting up stack guards.\n"); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; mainboard_romstage_entry(bist); /* Check the stack. */ for (i = 0; i < num_guards; i++) { if (stack_base[i] == stack_guard) continue; printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } /* Get the stack to use after cache-as-ram is torn down. */ romstage_stack_after_car = setup_romstage_stack_after_car(); return romstage_stack_after_car; }
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { void *top_of_stack; struct pei_data pei_data; struct romstage_params params = { .pei_data = &pei_data, .chipset_context = fih, }; post_code(0x30); timestamp_add_now(TS_START_ROMSTAGE); /* Load microcode before RAM init */ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); memset(&pei_data, 0, sizeof(pei_data)); /* Display parameters */ printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); /* Display FSP banner */ print_fsp_info(fih); /* Stash FSP version. */ params.fsp_version = fsp_version(fih); /* Get power state */ params.power_state = fill_power_state(); /* * Read and print board version. Done after SOC romstage * in case PCH needs to be configured to talk to the EC. */ if (IS_ENABLED(CONFIG_BOARD_ID_AUTO)) printk(BIOS_INFO, "MLB: board version %d\n", board_id()); /* Call into mainboard. */ mainboard_romstage_entry(¶ms); soc_after_ram_init(¶ms); post_code(0x38); top_of_stack = setup_stack_and_mtrrs(); printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); return top_of_stack; }
/* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) { struct romstage_params rp = { .bist = bist, .mrc_params = NULL, }; /* Save initial timestamp from bootblock. */ timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); /* Save romstage begin */ timestamp_add_now(TS_START_ROMSTAGE); program_base_addresses(); tco_disable(); byt_config_com1_and_enable(); console_init(); spi_init(); set_max_freq(); punit_init(); gfx_init(); #if CONFIG_EC_GOOGLE_CHROMEEC /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif /* Call into mainboard. */ mainboard_romstage_entry(&rp); return setup_stack_and_mttrs(); }
/* Entry from cache-as-ram.inc. */ void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) { struct romstage_params rp = { .bist = bist, .mrc_params = NULL, }; /* Save initial timestamp from bootblock. */ timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); /* Save romstage begin */ timestamp_add_now(TS_START_ROMSTAGE); program_base_addresses(); tco_disable(); byt_config_com1_and_enable(); console_init(); spi_init(); set_max_freq(); punit_init(); gfx_init(); /* Call into mainboard. */ mainboard_romstage_entry(&rp); platform_enter_postcar(); /* We don't return here */ return NULL; }
void * asmlinkage romstage_main(unsigned long bist) { mainboard_romstage_entry(bist); return (void*)CONFIG_RAMTOP; }