static _mali_osk_errcode_t enable_mali_clocks(struct device *dev) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); /* set clock rate */ #ifdef CONFIG_MALI_DVFS if (mali_dvfs_control != 0 || mali_gpu_clk >= mali_runtime_resume.clk) { mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); } else { #ifdef CONFIG_REGULATOR mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT)); #endif mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); set_mali_dvfs_current_step(mali_runtime_resume.step); } #else mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ); maliDvfsStatus.currentStep = MALI_DVFS_DEFAULT_STEP; #endif MALI_SUCCESS; }
static _mali_osk_errcode_t enable_mali_clocks(void) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); mali_runtime_resume.vol = mali_dvfs_get_vol(MALI_DVFS_STEPS + 1); #if MALI_PMM_RUNTIME_JOB_CONTROL_ON #if MALI_DVFS_ENABLED // set clock rate if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk) mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); else { mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); } if (mali_gpu_clk <= mali_runtime_resume.clk) set_mali_dvfs_current_step(MALI_DVFS_STEPS + 1); /* lock/unlock CPU freq by Mali */ if (mali_gpu_clk >= 533) err = cpufreq_lock_by_mali(1400); else if (mali_gpu_clk == 440) err = cpufreq_lock_by_mali(1200); #else mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); #endif #else mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); #endif MALI_SUCCESS; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; if (mali_step_lock > -1 && step != mali_step_lock) { step = mali_step_lock; } #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED #ifndef CONFIG_ABB_CONTROL if (samsung_rev() < EXYNOS4412_REV_2_0) { if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); } #else abb_target(ABB_G3D, mali_dvfs[step].clock*1000); #endif #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[step].clock == 440) err = cpufreq_lock_by_mali(1200); else cpufreq_unlock_by_mali(); #endif return MALI_TRUE; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount()==0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } maliDvfsStatus.currentStep = validatedStep; /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; return MALI_TRUE; }
static _mali_osk_errcode_t enable_mali_clocks(void) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); #if 0 #if MALI_DVFS_ENABLED // set clock rate if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk) mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); else { mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); set_mali_dvfs_current_step(MALI_DVFS_DEFAULT_STEP); } #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_gpu_clk >= 533) err = cpufreq_lock_by_mali(1200); else if (mali_gpu_clk == 440) err = cpufreq_lock_by_mali(1000); #endif #else mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); #endif #else mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); #endif MALI_SUCCESS; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; /* lock/unlock CPU freq by Mali */ /* if ((mali_dvfs[step].clock == 533) || (mali_dvfs[step].clock == 440)) #if defined(CONFIG_EXYNOS4X12_1800MHZ_SUPPORT) err = cpufreq_lock_by_mali(1800); #elif defined(CONFIG_EXYNOS4X12_1600MHZ_SUPPORT) err = cpufreq_lock_by_mali(1600); #elif defined(CONFIG_EXYNOS4X12_1500MHZ_SUPPORT) err = cpufreq_lock_by_mali(1500); #elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT) err = cpufreq_lock_by_mali(1400); #else err = cpufreq_lock_by_mali(1200); #endif else cpufreq_unlock_by_mali(); */ return MALI_TRUE; }
int change_dvfs_tableset(int change_clk, int change_step) { int err; if (change_clk < mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[0].clock; } else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[1].clock; } else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[2].clock; } else { mali_dvfs[change_step].clock = mali_dvfs_all[3].clock; } MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol)); if (maliDvfsStatus.currentStep == change_step) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq); #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[change_step].clock == 440) err = cpufreq_lock_by_mali(1200); else cpufreq_unlock_by_mali(); #endif } return mali_dvfs[change_step].clock; }
void mali_default_step_set(int step, mali_bool boostup) { mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); if (maliDvfsStatus.currentStep == 1) set_mali_dvfs_status(step, boostup); }
int mali_dvfs_bottom_lock_push(int lock_step) { int prev_status = _mali_osk_atomic_read(&bottomlock_status); if (prev_status < 0) { MALI_PRINT(("gpu bottom lock status is not valid for push\n")); return -1; } // not a bad idea to limit locking to 4th step, so let's leave this -gm if (samsung_rev() < EXYNOS4412_REV_2_0) lock_step = min(lock_step, MALI_DVFS_STEPS - 2); else lock_step = min(lock_step, MALI_DVFS_STEPS - 1); if (bottom_lock_step < lock_step) { bottom_lock_step = lock_step; if (get_mali_dvfs_status() < lock_step) { mali_regulator_set_voltage(mali_dvfs[lock_step].vol, mali_dvfs[lock_step].vol); mali_clk_set_rate(mali_dvfs[lock_step].clock, mali_dvfs[lock_step].freq); set_mali_dvfs_current_step(lock_step); } } return _mali_osk_atomic_inc_return(&bottomlock_status); }
void mali_force_mpll(void) { mali_use_vpll_save = mali_use_vpll; mali_use_vpll = false; mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); }
int change_dvfs_tableset(int change_clk, int change_step) { if (change_clk < mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[0].clock; mali_dvfs[change_step].vol = mali_dvfs[0].vol; } else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[1].clock; mali_dvfs[change_step].vol = mali_dvfs[1].vol; } else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[2].clock; mali_dvfs[change_step].vol = mali_dvfs[2].vol; } else { mali_dvfs[change_step].clock = mali_dvfs_all[3].clock; mali_dvfs[change_step].vol = mali_dvfs[3].vol; } MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol)); if (maliDvfsStatus.currentStep == change_step) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq); } return mali_dvfs[change_step].clock; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; if (mali_clock != 0) return ret; // already initialized mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE) { ret = MALI_FALSE; goto err_clock_get; } MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock)); #ifdef CONFIG_REGULATOR #if USING_MALI_PMM g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d"); #else g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } regulator_enable(g3d_regulator); MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); #endif MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n")); MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__)); MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock - normal\n", __FUNCTION__)); mali_clk_put(MALI_FALSE); gpu_power_state = 0; bPoweroff = 1; return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clock_get: mali_clk_put(MALI_TRUE); return ret; }
static _mali_osk_errcode_t enable_mali_clocks(void) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); // set clock rate if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk) mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); else { mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol); mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ); } if (mali_gpu_clk <= mali_runtime_resume.clk) set_mali_dvfs_current_step(7); MALI_SUCCESS; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[step].clock >= 533) err = cpufreq_lock_by_mali(1200); else if (mali_dvfs[step].clock == 440) err = cpufreq_lock_by_mali(1000); else cpufreq_unlock_by_mali(); #endif return MALI_TRUE; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED if (samsung_rev() < EXYNOS4412_REV_2_0) { if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); } #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; return MALI_TRUE; }
static _mali_osk_errcode_t enable_mali_clocks(void) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); // set clock rate mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); MALI_SUCCESS; }
static _mali_osk_errcode_t enable_mali_clocks(void) { int err; err = clk_enable(mali_clock); MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err)); // set clock rate mali_clk_set_rate(mali_gpu_clk, GPU_MHZ); /* lock/unlock CPU freq by Mali */ if (mali_gpu_clk >= 300) err = cpufreq_lock_by_mali(800); MALI_SUCCESS; }
int mali_dvfs_bottom_lock_push(void) { int prev_status = _mali_osk_atomic_read(&bottomlock_status); if (prev_status < 0) { MALI_PRINT(("gpu bottom lock status is not valid for push")); return -1; } if (prev_status == 0) { mali_regulator_set_voltage(mali_dvfs[1].vol, mali_dvfs[1].vol); mali_clk_set_rate(mali_dvfs[1].clock, mali_dvfs[1].freq); set_mali_dvfs_current_step(1); } return _mali_osk_atomic_inc_return(&bottomlock_status); }
int mali_dvfs_bottom_lock_push(int lock_step) { int prev_status = _mali_osk_atomic_read(&bottomlock_status); if (prev_status < 0) { MALI_PRINT(("gpu bottom lock status is not valid for push\n")); return -1; } if (bottom_lock_step < lock_step) { bottom_lock_step = lock_step; if (get_mali_dvfs_status() < lock_step) { mali_regulator_set_voltage(mali_dvfs[lock_step].vol, mali_dvfs[lock_step].vol); mali_clk_set_rate(mali_dvfs[lock_step].clock, mali_dvfs[lock_step].freq); set_mali_dvfs_current_step(lock_step); } } return _mali_osk_atomic_inc_return(&bottomlock_status); }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; if (mali_clock != 0 || mali_clock_pd != 0) return ret; mali_clock_pd = mali_clk_get(GPUCLK_PD_NAME); if (IS_ERR(mali_clock_pd)) { MALI_PRINT( ("MALI Error : failed to get source mali pd\n")); ret = MALI_FALSE; goto err_gpu_clk; } enable_mali_clocks(mali_clock_pd); mali_clock = mali_clk_get(GPUCLK_NAME); if (IS_ERR(mali_clock)) { MALI_PRINT( ("MALI Error : failed to get source mali clock\n")); ret = MALI_FALSE; goto err_gpu_clk; } enable_mali_clocks(mali_clock); mali_clk_set_rate(mali_clock, mali_init_clock); MALI_PRINT(("init mali clock success\n")); return MALI_TRUE; err_gpu_clk: MALI_PRINT(("::clk_put:: %s mali_clock\n", __FUNCTION__)); clk_put(mali_clock_pd); clk_put(mali_clock); mali_clock = 0; mali_clock_pd = 0; return ret; }
static mali_bool init_mali_clock(void) { int err = 0; mali_bool ret = MALI_TRUE; nPowermode = MALI_POWER_MODE_DEEP_SLEEP; if (mali_clock != 0) return ret; /* already initialized */ mali_freq_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_freq_lock == NULL) return _MALI_OSK_ERR_FAULT; if (!mali_clk_get()) { MALI_PRINT(("Error: Failed to get Mali clock\n")); goto err_clk; } #ifndef CONFIG_EXYNOS3_VPLL err = clk_set_parent(mali_mout0_clock, sclk_mpll_pre_div_clock); if (err) MALI_PRINT_ERROR(("mali_mout0_clock set parent to sclk_mpll_pre_div_clock failed\n")); err = clk_set_parent(mali_clock, mali_mout0_clock); if (err) MALI_PRINT_ERROR(("mali_clock set parent to mali_mout0_clock failed\n")); #else err = clk_set_rate(fout_vpll_clock, (unsigned int)mali_gpu_clk * GPU_MHZ); if (err > 0) MALI_PRINT_ERROR(("Failed to set fout_vpll clock: %d\n", err)); err = clk_set_parent(vpll_src_clock, ext_xtal_clock); if (err) MALI_PRINT_ERROR(("vpll_src_clock set parent to ext_xtal_clock failed\n")); err = clk_set_parent(sclk_vpll_clock, fout_vpll_clock); if (err) MALI_PRINT_ERROR(("sclk_vpll_clock set parent to fout_vpll_clock failed\n")); err = clk_set_parent(mali_mout1_clock, sclk_vpll_clock); if (err) MALI_PRINT_ERROR(("mali_mout1_clock set parent to sclk_vpll_clock failed\n")); err = clk_set_parent(mali_clock, mali_mout1_clock); if (err) MALI_PRINT_ERROR(("mali_clock set parent to mali_mout1_clock failed\n")); #endif if (!atomic_read(&clk_active)) { if (clk_enable(mali_clock) < 0) { MALI_PRINT(("Error: Failed to enable clock\n")); goto err_clk; } atomic_set(&clk_active, 1); } mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ); mali_clk_put(MALI_FALSE); return MALI_TRUE; err_clk: mali_clk_put(MALI_TRUE); return ret; }
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { unsigned int nextStatus = (unsigned int)*freq; unsigned int curStatus = 0; curStatus = maliDvfsStatus.currentStep; MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep)); /*if next status is same with current status, don't change anything*/ if (curStatus != nextStatus) { #if MALI_DVFS_CLK_DEBUG unsigned int *pRegMaliClkDiv; unsigned int *pRegMaliMpll; #endif if (nextStatus > curStatus) { #ifdef CONFIG_MALI_DVFS update_time_in_state(curStatus); #endif #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq); } else if (nextStatus < curStatus) { #ifdef CONFIG_MALI_DVFS update_time_in_state(curStatus); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT)); #endif } else return 0; #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE| MALI_PROFILING_EVENT_CHANNEL_GPU| MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0); #endif mali_clk_put(MALI_FALSE); #if MALI_DVFS_CLK_DEBUG pRegMaliClkDiv = ioremap(0x1003c52c, 32); pRegMaliMpll = ioremap(0x1003c22c, 32); MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv)); #endif set_mali_dvfs_current_step(nextStatus); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[nextStatus].clock >= 440) cpufreq_lock_by_mali(400); else cpufreq_unlock_by_mali(); #endif /*wait until clock and voltage is stablized*/ mali_platform_wating(MALI_DVFS_WATING); /*msec*/ } return 0; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; nPowermode = MALI_POWER_MODE_DEEP_SLEEP; if (mali_clock != 0) return ret; /* already initialized */ mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (!mali_clk_get()) { MALI_PRINT(("Error: Failed to get Mali clock\n")); goto err_clk; } clk_set_parent(vpll_src_clock, ext_xtal_clock); clk_set_parent(sclk_vpll_clock, fout_vpll_clock); clk_set_parent(mali_parent_clock, sclk_vpll_clock); clk_set_parent(mali_clock, mali_parent_clock); if (!atomic_read(&clk_active)) { if (clk_enable(mali_clock) < 0) { MALI_PRINT(("Error: Failed to enable clock\n")); goto err_clk; } atomic_set(&clk_active, 1); } mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ); MALI_PRINT(("init_mali_clock mali_clock %x\n", mali_clock)); #ifdef CONFIG_REGULATOR g3d_regulator = regulator_get(NULL, "vdd_g3d"); if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } mali_gpu_vol = get_match_volt(ID_G3D, mali_gpu_clk * GPU_ASV_VOLT); mali_runtime_resume.vol = get_match_volt(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT); regulator_enable(g3d_regulator); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT)); #endif #if defined(CONFIG_MALI400_PROFILING) _mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE| MALI_PROFILING_EVENT_CHANNEL_GPU| MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0); #endif mali_clk_put(MALI_FALSE); return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clk: mali_clk_put(MALI_TRUE); return ret; }