_mali_osk_errcode_t mali_platform_init(void) { mali_clk = clk_get_sys("mali", "pll_fixed"); if (mali_clk ) { if (!mali_init_flag) { #if defined(CONFIG_MALI_CLK_400M) clk_set_rate(mali_clk, 400000000); #elif defined(CONFIG_MALI_CLK_333M) clk_set_rate(mali_clk, 333000000); #else clk_set_rate(mali_clk, 250000000); #endif mali_clk->enable(mali_clk); malifix_init(); mali_meson_poweron(1); mali_init_flag = 1; } MALI_SUCCESS; } #ifdef CONFIG_ARCH_MESON6 MALI_PRINT_ERROR(("Failed to lookup mali clock")); MALI_ERROR(_MALI_OSK_ERR_FAULT); #else MALI_SUCCESS; #endif /* CONFIG_ARCH_MESON6 */ }
_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode) { /* turn off MALI clock gating */ unsigned long flags; unsigned cpu_divider, mali_divider; unsigned ddr_pll_setting, sys_pll_setting; unsigned cpu_freq, ddr_freq; int mali_flag; switch (power_mode) { case MALI_POWER_MODE_LIGHT_SLEEP: /* turn on MALI clock gating */ CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8); break; case MALI_POWER_MODE_DEEP_SLEEP: /* turn on MALI clock gating */ CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8); break; case MALI_POWER_MODE_ON: /* turn off MALI clock gating */ local_irq_save(flags); CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8); sys_pll_setting = READ_MPEG_REG(HHI_SYS_PLL_CNTL); cpu_freq = ((sys_pll_setting&0x1ff)*24)>>(sys_pll_setting>>16); // assume 24M xtal cpu_divider = READ_MPEG_REG_BITS(HHI_SYS_CPU_CLK_CNTL, 2, 2); if (cpu_divider == 3) cpu_divider = 2; // now fix at /4 cpu_freq >>= cpu_divider; ddr_pll_setting = READ_MPEG_REG(HHI_DDR_PLL_CNTL); ddr_freq = ((ddr_pll_setting&0x1ff)*24)>>((ddr_pll_setting>>16)&3); mali_divider = 1; while ((mali_divider * cpu_freq < ddr_freq) || (264 * mali_divider < ddr_freq)) // assume mali max 264M mali_divider++; mali_flag = ((mali_divider-1) != (READ_MPEG_REG(HHI_MALI_CLK_CNTL)&0x7f)); if (mali_flag){ WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, (3 << 9) | // select ddr pll as clock source ((mali_divider-1) << 0)); // ddr clk / divider READ_CBUS_REG(HHI_MALI_CLK_CNTL); // delay } SET_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8); local_irq_restore(flags); if (mali_flag) printk("(CTS_MALI_CLK) = %d/%d = %dMHz --- when mali gate on\n", ddr_freq, mali_divider, ddr_freq/mali_divider); mali_meson_poweron(); break; } last_power_mode = power_mode; MALI_SUCCESS; }
_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode) { MALI_DEBUG_PRINT(3, ( "mali_platform_power_mode_change power_mode=%d\n", power_mode)); switch (power_mode) { case MALI_POWER_MODE_LIGHT_SLEEP: case MALI_POWER_MODE_DEEP_SLEEP: /* Turn off mali clock gating */ mali_clk->disable(mali_clk); break; case MALI_POWER_MODE_ON: /* Turn on MALI clock gating */ mali_clk->enable(mali_clk); mali_meson_poweron(0); break; } last_power_mode = power_mode; MALI_SUCCESS; }
_mali_osk_errcode_t mali_platform_init(void) { mali_clk = clk_get_sys("mali", "pll_fixed"); if (mali_clk ) { if (!mali_init_flag) { clk_set_rate(mali_clk, 400000000); mali_clk->enable(mali_clk); malifix_init(); mali_meson_poweron(1); mali_init_flag = 1; } MALI_SUCCESS; } else panic("linux kernel should > 3.0\n"); #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 MALI_PRINT_ERROR(("Failed to lookup mali clock")); MALI_ERROR(_MALI_OSK_ERR_FAULT); #else MALI_SUCCESS; #endif /* CONFIG_ARCH_MESON6 */ }