static mali_bool change_mali_dvfs_status(u32 step, mali_bool boostup )
{
MALI_DEBUG_PRINT(1, ("> change_mali_dvfs_status: %d, %d \n",step, boostup));
if (!set_mali_dvfs_status(step, boostup)) {
MALI_DEBUG_PRINT(1, ("error on set_mali_dvfs_status: %d, %d \n",step, boostup));
return MALI_FALSE;
}
/*wait until clock and voltage is stablized*/
mali_platform_wating(MALI_DVFS_WATING); /*msec*/
return MALI_TRUE;
}
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
unsigned int nextStatus = (unsigned int)*freq;
unsigned int curStatus = 0;
curStatus = maliDvfsStatus.currentStep;
MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));
/*if next status is same with current status, don't change anything*/
if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
unsigned int *pRegMaliClkDiv;
unsigned int *pRegMaliMpll;
#endif
if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
} else
return 0;
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
#if MALI_DVFS_CLK_DEBUG
pRegMaliClkDiv = ioremap(0x1003c52c, 32);
pRegMaliMpll = ioremap(0x1003c22c, 32);
MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
set_mali_dvfs_current_step(nextStatus);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];
#if CPUFREQ_LOCK_DURING_440
/* lock/unlock CPU freq by Mali */
if (mali_dvfs[nextStatus].clock >= 440)
cpufreq_lock_by_mali(400);
else
cpufreq_unlock_by_mali();
#endif
/*wait until clock and voltage is stablized*/
mali_platform_wating(MALI_DVFS_WATING); /*msec*/
}
return 0;
}