static void mali_group_recovery_reset(struct mali_group *group)
{
MALI_ASSERT_GROUP_LOCKED(group);
/* Stop cores, bus stop */
if (NULL != group->pp_core)
{
mali_pp_stop_bus(group->pp_core);
}
if (NULL != group->gp_core)
{
mali_gp_stop_bus(group->gp_core);
}
/* Flush MMU */
mali_mmu_activate_fault_flush_page_directory(group->mmu);
mali_mmu_page_fault_done(group->mmu);
/* Wait for cores to stop bus */
if (NULL != group->pp_core)
{
mali_pp_stop_bus_wait(group->pp_core);
}
if (NULL != group->gp_core)
{
mali_gp_stop_bus_wait(group->gp_core);
}
/* Reset cores */
if (NULL != group->pp_core)
{
mali_pp_hard_reset(group->pp_core);
}
if (NULL != group->gp_core)
{
mali_gp_hard_reset(group->gp_core);
}
/* Reset MMU */
mali_mmu_reset(group->mmu);
group->session = NULL;
}
_mali_osk_errcode_t mali_pp_reset(struct mali_pp_core *core)
{
int i;
const int request_loop_count = 20;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_DEBUG_PRINT(4, ("Mali PP: Reset of core %s\n", core->hw_core.description));
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_pp_post_process_job(core); /* @@@@?is there some cases where it is unsafe to post process the job here? */
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, 0); /* disable the IRQs */
#if defined(USING_MALI200)
/* On Mali-200, stop the bus, then do a hard reset of the core */
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_STOP_BUS);
for (i = 0; i < request_loop_count; i++)
{
if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS) & MALI200_REG_VAL_STATUS_BUS_STOPPED)
{
break;
}
_mali_osk_time_ubusydelay(10);
}
if (request_loop_count == i)
{
MALI_PRINT_ERROR(("Mali PP: Failed to stop bus for core %s, unable to recover\n", core->hw_core.description));
return _MALI_OSK_ERR_FAULT ;
}
/* the bus was stopped OK, do the hard reset */
mali_pp_hard_reset(core);
#elif defined(USING_MALI400)
/* Mali-300 and Mali-400 have a safe reset command which we use */
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI400PP_REG_VAL_IRQ_RESET_COMPLETED);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET);
for (i = 0; i < request_loop_count; i++)
{
if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & MALI400PP_REG_VAL_IRQ_RESET_COMPLETED)
{
break;
}
_mali_osk_time_ubusydelay(10);
}
if (request_loop_count == i)
{
MALI_DEBUG_PRINT(2, ("Mali PP: Failed to reset core %s, Status: 0x%08x\n", core->hw_core.description, mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS)));
return _MALI_OSK_ERR_FAULT;
}
#else
#error "no supported mali core defined"
#endif
/* Re-enable interrupts */
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_MASK_ALL);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED);
return _MALI_OSK_ERR_OK;
}
_mali_osk_errcode_t mali_pp_reset(struct mali_pp_core *core)
{
int i;
const int request_loop_count = 20;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_DEBUG_PRINT(4, ("Mali PP: Reset of core %s\n", core->hw_core.description));
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_pp_post_process_job(core);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, 0);
#if defined(USING_MALI200)
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_STOP_BUS);
for (i = 0; i < request_loop_count; i++)
{
if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS) & MALI200_REG_VAL_STATUS_BUS_STOPPED)
{
break;
}
_mali_osk_time_ubusydelay(10);
}
if (request_loop_count == i)
{
MALI_PRINT_ERROR(("Mali PP: Failed to stop bus for core %s, unable to recover\n", core->hw_core.description));
return _MALI_OSK_ERR_FAULT ;
}
mali_pp_hard_reset(core);
#elif defined(USING_MALI400)
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI400PP_REG_VAL_IRQ_RESET_COMPLETED);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET);
for (i = 0; i < request_loop_count; i++)
{
if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & MALI400PP_REG_VAL_IRQ_RESET_COMPLETED)
{
break;
}
_mali_osk_time_ubusydelay(10);
}
if (request_loop_count == i)
{
MALI_DEBUG_PRINT(2, ("Mali PP: Failed to reset core %s, Status: 0x%08x\n", core->hw_core.description, mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS)));
return _MALI_OSK_ERR_FAULT;
}
#else
#error "no supported mali core defined"
#endif
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_MASK_ALL);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED);
return _MALI_OSK_ERR_OK;
}
