static int omap_hsmmc_set_ios(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
#else
static int omap_hsmmc_set_ios(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
#endif
struct hsmmc *mmc_base;
unsigned int dsor = 0;
ulong start;
mmc_base = priv->base_addr;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
&mmc_base->con);
break;
case 4:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
&mmc_base->hctl);
break;
case 1:
default:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
&mmc_base->hctl);
break;
}
/* configure clock with 96Mhz system clock.
*/
if (mmc->clock != 0) {
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
dsor++;
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
return -ETIMEDOUT;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
return 0;
}
#ifdef OMAP_HSMMC_USE_GPIO
#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->cd_gpio);
/* if no CD return as 1 */
if (value < 0)
return 1;
if (priv->cd_inverted)
return !value;
return value;
}
static int omap_hsmmc_getwp(struct udevice *dev)
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value;
value = dm_gpio_get_value(&priv->wp_gpio);
/* if no WP return as 0 */
if (value < 0)
return 0;
return value;
}
#else
static int omap_hsmmc_getcd(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int cd_gpio;
/* if no CD return as 1 */
cd_gpio = priv->cd_gpio;
if (cd_gpio < 0)
return 1;
/* NOTE: assumes card detect signal is active-low */
return !gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
{
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
int wp_gpio;
/* if no WP return as 0 */
wp_gpio = priv->wp_gpio;
if (wp_gpio < 0)
return 0;
/* NOTE: assumes write protect signal is active-high */
return gpio_get_value(wp_gpio);
}
#endif
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
static const struct dm_mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
#ifdef OMAP_HSMMC_USE_GPIO
.get_cd = omap_hsmmc_getcd,
.get_wp = omap_hsmmc_getwp,
#endif
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
.send_cmd = omap_hsmmc_send_cmd,
.set_ios = omap_hsmmc_set_ios,
.init = omap_hsmmc_init_setup,
#ifdef OMAP_HSMMC_USE_GPIO
.getcd = omap_hsmmc_getcd,
.getwp = omap_hsmmc_getwp,
#endif
};
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio)
{
struct mmc *mmc;
struct omap_hsmmc_data *priv;
struct mmc_config *cfg;
uint host_caps_val;
priv = malloc(sizeof(*priv));
if (priv == NULL)
return -1;
host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
break;
#endif
default:
priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
#ifdef OMAP_HSMMC_USE_GPIO
/* on error gpio values are set to -1, which is what we want */
priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
#endif
cfg = &priv->cfg;
cfg->name = "OMAP SD/MMC";
cfg->ops = &omap_hsmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = host_caps_val & ~host_caps_mask;
cfg->f_min = 400000;
if (f_max != 0)
cfg->f_max = f_max;
else {
if (cfg->host_caps & MMC_MODE_HS) {
if (cfg->host_caps & MMC_MODE_HS_52MHz)
cfg->f_max = 52000000;
else
cfg->f_max = 26000000;
} else
cfg->f_max = 20000000;
}
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
cfg->b_max = 1;
#endif
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
return 0;
}
#else
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_config *cfg = &plat->cfg;
struct omap2_mmc_platform_config *data =
(struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int val;
plat->base_addr = map_physmem(devfdt_get_addr(dev),
sizeof(struct hsmmc *),
MAP_NOCACHE) + data->reg_offset;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
val = fdtdec_get_int(fdt, node, "bus-width", -1);
if (val < 0) {
printf("error: bus-width property missing\n");
return -ENOENT;
}
switch (val) {
case 0x8:
cfg->host_caps |= MMC_MODE_8BIT;
case 0x4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
default:
printf("error: invalid bus-width property\n");
return -ENOENT;
}
cfg->f_min = 400000;
cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
#ifdef OMAP_HSMMC_USE_GPIO
plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
#endif
return 0;
}
#endif
#ifdef CONFIG_BLK
static int omap_hsmmc_bind(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#endif
static int omap_hsmmc_probe(struct udevice *dev)
{
struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct omap_hsmmc_data *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
struct mmc *mmc;
cfg->name = "OMAP SD/MMC";
priv->base_addr = plat->base_addr;
#ifdef OMAP_HSMMC_USE_GPIO
priv->cd_inverted = plat->cd_inverted;
#endif
#ifdef CONFIG_BLK
mmc = &plat->mmc;
#else
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
#endif
#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
mmc->dev = dev;
upriv->mmc = mmc;
return omap_hsmmc_init_setup(mmc);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
.reg_offset = 0,
};
static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
.reg_offset = 0x100,
};
static const struct udevice_id omap_hsmmc_ids[] = {
{
.compatible = "ti,omap3-hsmmc",
.data = (ulong)&omap3_mmc_pdata
},
{
.compatible = "ti,omap4-hsmmc",
.data = (ulong)&omap4_mmc_pdata
},
{
.compatible = "ti,am33xx-hsmmc",
.data = (ulong)&am33xx_mmc_pdata
},
{ }
};
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
int err;
/* try Processor Local Bus device first */
addr = dev_read_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
dev_of_offset(dev),
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
return ret;
}
ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
addr = bar;
}
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = addr;
#else
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
plat->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("ns16550 failed to get clock\n");
return err;
}
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
plat->fcr = UART_FCR_DEFVAL;
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
return 0;
}
static int ehci_usb_probe(struct udevice *dev)
{
struct generic_ehci *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int i, err, ret, clock_nb, reset_nb;
err = 0;
priv->clock_count = 0;
clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
"#clock-cells");
if (clock_nb > 0) {
priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
GFP_KERNEL);
if (!priv->clocks)
return -ENOMEM;
for (i = 0; i < clock_nb; i++) {
err = clk_get_by_index(dev, i, &priv->clocks[i]);
if (err < 0)
break;
err = clk_enable(&priv->clocks[i]);
if (err) {
pr_err("failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
}
priv->clock_count++;
}
} else {
if (clock_nb != -ENOENT) {
pr_err("failed to get clock phandle(%d)\n", clock_nb);
return clock_nb;
}
}
priv->reset_count = 0;
reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
"#reset-cells");
if (reset_nb > 0) {
priv->resets = devm_kcalloc(dev, reset_nb,
sizeof(struct reset_ctl),
GFP_KERNEL);
if (!priv->resets)
return -ENOMEM;
for (i = 0; i < reset_nb; i++) {
err = reset_get_by_index(dev, i, &priv->resets[i]);
if (err < 0)
break;
if (reset_deassert(&priv->resets[i])) {
pr_err("failed to deassert reset %d\n", i);
reset_free(&priv->resets[i]);
goto reset_err;
}
priv->reset_count++;
}
} else {
if (reset_nb != -ENOENT) {
pr_err("failed to get reset phandle(%d)\n", reset_nb);
goto clk_err;
}
}
err = generic_phy_get_by_index(dev, 0, &priv->phy);
if (err) {
if (err != -ENOENT) {
pr_err("failed to get usb phy\n");
goto reset_err;
}
} else {
err = generic_phy_init(&priv->phy);
if (err) {
pr_err("failed to init usb phy\n");
goto reset_err;
}
}
hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
err = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
if (err)
goto phy_err;
return 0;
phy_err:
if (generic_phy_valid(&priv->phy)) {
ret = generic_phy_exit(&priv->phy);
if (ret)
pr_err("failed to release phy\n");
}
reset_err:
ret = reset_release_all(priv->resets, priv->reset_count);
if (ret)
pr_err("failed to assert all resets\n");
clk_err:
ret = clk_release_all(priv->clocks, priv->clock_count);
if (ret)
pr_err("failed to disable all clocks\n");
return err;
}
void ddr_tap_tuning(void)
{
void __iomem *regs;
u32 *addr_k0, *addr_k1, *addr;
u32 val, tap, upper, lower;
int i, j, dir, err, done;
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
/* Init memory pattern */
addr = (void *)CKSEG0ADDR(0x2000);
for (i = 0; i < 256; i++) {
val = 0;
for (j = 0; j < 8; j++) {
if (i & (1 << j)) {
if (j % 2)
val |= 0xffff0000;
else
val |= 0x0000ffff;
}
if (j % 2) {
*addr++ = val;
val = 0;
}
}
}
err = 0;
done = 0;
dir = 1;
tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
val = tap;
upper = tap;
lower = tap;
while (!done) {
err = 0;
/* Update new DDR tap value */
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* Compare DDR with cache */
for (i = 0; i < 2; i++) {
addr_k1 = (void *)CKSEG1ADDR(0x2000);
addr_k0 = (void *)CKSEG0ADDR(0x2000);
addr = (void *)CKSEG0ADDR(0x3000);
while (addr_k0 < addr) {
if (*addr_k1++ != *addr_k0++) {
err = 1;
break;
}
}
if (err)
break;
}
if (err) {
/* Save upper/lower threshold if error */
if (dir) {
dir = 0;
val--;
upper = val;
val = tap;
} else {
val++;
lower = val;
done = 1;
}
} else {
/* Try the next value until limitation */
if (dir) {
if (val < 0x20) {
val++;
} else {
dir = 0;
upper = val;
val = tap;
}
} else {
if (!val) {
lower = val;
done = 1;
} else {
val--;
}
}
}
}
/* compute an intermediate value and write back */
val = (upper + lower) / 2;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
val++;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
}
void ddr_init(void)
{
void __iomem *regs;
u32 val;
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
val = ath79_get_bootstrap();
if (val & AR933X_BOOTSTRAP_DDR2) {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
/* Enable DDR2 */
writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Disable High Temperature Self-Refresh, Full Array */
writel(0x00, regs + AR933X_DDR_REG_EMR2);
/* Extended Mode Register 2 Set (EMR2S) */
writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
writel(0x00, regs + AR933X_DDR_REG_EMR3);
/* Extended Mode Register 3 Set (EMR3S) */
writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
/* Enable DLL, Full strength, ODT Disabled */
writel(0x00, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Reset DLL */
writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Auto Refresh */
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Refresh time control */
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
writel(DDR_REFRESH_VAL_40M, regs +
AR71XX_DDR_REG_REFRESH);
else
writel(DDR_REFRESH_VAL_25M, regs +
AR71XX_DDR_REG_REFRESH);
/* DQS 0 Tap Control */
writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
/* DQS 1 Tap Control */
writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* For 16-bit DDR */
writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
} else {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Reset DLL, Burst Length 8, CAS Latency 3 */
writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
/* Forces an MRS update cycle in DDR */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Enable DLL, Full strength */
writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Normal DLL, Burst Length 8, CAS Latency 3 */
writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Refresh time control */
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
writel(DDR_REFRESH_VAL_40M, regs +
AR71XX_DDR_REG_REFRESH);
else
writel(DDR_REFRESH_VAL_25M, regs +
AR71XX_DDR_REG_REFRESH);
/* DQS 0 Tap Control */
writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
/* DQS 1 Tap Control */
writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* For 16-bit DDR */
writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
}
}
static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
{
struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
return 0;
}
static int altera_tse_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev->of_offset;
const char *list, *end;
const fdt32_t *cell;
void *base, *desc_mem = NULL;
unsigned long addr, size;
int parent, addrc, sizec;
int len, idx;
int ret;
priv->dma_type = dev_get_driver_data(dev);
if (priv->dma_type == ALT_SGDMA)
priv->ops = &tse_sgdma_ops;
else
priv->ops = &tse_msgdma_ops;
/*
* decode regs. there are multiple reg tuples, and they need to
* match with reg-names.
*/
parent = fdt_parent_offset(blob, node);
of_bus_default_count_cells(blob, parent, &addrc, &sizec);
list = fdt_getprop(blob, node, "reg-names", &len);
if (!list)
return -ENOENT;
end = list + len;
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell)
return -ENOENT;
idx = 0;
while (list < end) {
addr = fdt_translate_address((void *)blob,
node, cell + idx);
size = fdt_addr_to_cpu(cell[idx + addrc]);
base = map_physmem(addr, size, MAP_NOCACHE);
len = strlen(list);
if (strcmp(list, "control_port") == 0)
priv->mac_dev = base;
else if (strcmp(list, "rx_csr") == 0)
priv->sgdma_rx = base;
else if (strcmp(list, "rx_desc") == 0)
priv->rx_desc = base;
else if (strcmp(list, "rx_resp") == 0)
priv->rx_resp = base;
else if (strcmp(list, "tx_csr") == 0)
priv->sgdma_tx = base;
else if (strcmp(list, "tx_desc") == 0)
priv->tx_desc = base;
else if (strcmp(list, "s1") == 0)
desc_mem = base;
idx += addrc + sizec;
list += (len + 1);
}
/* decode fifo depth */
priv->rx_fifo_depth = fdtdec_get_int(blob, node,
"rx-fifo-depth", 0);
priv->tx_fifo_depth = fdtdec_get_int(blob, node,
"tx-fifo-depth", 0);
/* decode phy */
addr = fdtdec_get_int(blob, node,
"phy-handle", 0);
addr = fdt_node_offset_by_phandle(blob, addr);
priv->phyaddr = fdtdec_get_int(blob, addr,
"reg", 0);
/* init desc */
if (priv->dma_type == ALT_SGDMA) {
len = sizeof(struct alt_sgdma_descriptor) * 4;
if (!desc_mem) {
desc_mem = dma_alloc_coherent(len, &addr);
if (!desc_mem)
return -ENOMEM;
}
memset(desc_mem, 0, len);
priv->tx_desc = desc_mem;
priv->rx_desc = priv->tx_desc +
2 * sizeof(struct alt_sgdma_descriptor);
}
/* allocate recv packet buffer */
priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
if (!priv->rx_buf)
return -ENOMEM;
/* stop controller */
debug("Reset TSE & SGDMAs\n");
altera_tse_stop(dev);
/* start the phy */
priv->interface = pdata->phy_interface;
tse_mdio_init(dev->name, priv);
priv->bus = miiphy_get_dev_by_name(dev->name);
ret = tse_phy_init(priv, dev);
return ret;
}
static int do_syno_populate(int argc, char * const argv[])
{
unsigned int bus = CONFIG_SF_DEFAULT_BUS;
unsigned int cs = CONFIG_SF_DEFAULT_CS;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
struct spi_flash *flash;
unsigned long addr = 0x80000; /* XXX: parameterize this? */
loff_t offset = 0x007d0000;
loff_t len = 0x00010000;
char *buf, *bufp;
char var[128];
char val[128];
int ret, n;
/* XXX: arg parsing to select flash here? */
flash = spi_flash_probe(bus, cs, speed, mode);
if (!flash) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
buf = map_physmem(addr, len, MAP_WRBACK);
if (!buf) {
puts("Failed to map physical memory\n");
return 1;
}
ret = spi_flash_read(flash, offset, len, buf);
if (ret) {
puts("Failed to read from SPI flash\n");
goto out_unmap;
}
for (n = 0; n < ETHADDR_MAX; n++) {
char ethaddr[ETH_ALEN];
int i, sum = 0;
unsigned char csum = 0;
for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) {
sum += bufp[i];
csum += bufp[i];
ethaddr[i] = bufp[i];
}
if (!sum) /* MAC address empty */
continue;
if (csum != bufp[i]) { /* seventh byte is checksum value */
printf("Invalid MAC address for interface %d!\n", n);
continue;
}
if (n == 0)
sprintf(var, "ethaddr");
else
sprintf(var, "eth%daddr", n);
snprintf(val, sizeof(val) - 1,
"%02x:%02x:%02x:%02x:%02x:%02x",
ethaddr[0], ethaddr[1], ethaddr[2],
ethaddr[3], ethaddr[4], ethaddr[5]);
printf("parsed %s = %s\n", var, val);
setenv(var, val);
}
if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) {
char *snp, *csump;
int csum = 0;
unsigned long c;
snp = bufp = buf + 32 + strlen(SYNO_SN_TAG);
for (n = 0; bufp[n] && bufp[n] != ','; n++)
csum += bufp[n];
bufp[n] = '\0';
/* should come right after, but you never know */
bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG);
if (!bufp) {
printf("Serial number checksum tag missing!\n");
goto out_unmap;
}
csump = bufp += strlen(SYNO_CHKSUM_TAG);
for (n = 0; bufp[n] && bufp[n] != ','; n++)
;
bufp[n] = '\0';
if (strict_strtoul(csump, 10, &c) || c != csum) {
puts("Invalid serial number found!\n");
ret = 1;
goto out_unmap;
}
printf("parsed SN = %s\n", snp);
setenv("SN", snp);
} else { /* old style format */
unsigned char csum = 0;
for (n = 0, bufp = buf + 32; n < 10; n++)
csum += bufp[n];
if (csum != bufp[n]) {
puts("Invalid serial number found!\n");
ret = 1;
goto out_unmap;
}
bufp[n] = '\0';
printf("parsed SN = %s\n", buf + 32);
setenv("SN", buf + 32);
}
out_unmap:
unmap_physmem(buf, len);
return ret;
}
