void extcl_cpu_wr_mem_164(WORD address, BYTE value) {
switch (address & 0x7300) {
case 0x5000:
m164.prg = (m164.prg & 0xF0) | (value & 0x0F);
value = m164.prg;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
return;
case 0x5100:
m164.prg = (m164.prg & 0x0F) | (value << 4);
value = m164.prg;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
return;
/*
case 0x5200:
return;
case 0x5300:
value = m164.prg;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
return;
*/
}
}
void extcl_cpu_wr_mem_91(WORD address, BYTE value) {
if (address < 0x6000) {
return;
}
if (address <= 0x6FFF) {
DBWORD bank;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
switch (address & 0x0003) {
case 0:
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
case 1:
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
case 2:
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
case 3:
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
}
}
if (address < 0x7FFF) {
switch (address & 0x0003) {
case 0:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
map_prg_rom_8k_update();
return;
case 1:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
return;
case 2:
m91.irq.active = 0;
m91.irq.count = 0;
irq.high &= ~EXT_IRQ;
return;
case 3:
m91.irq.active = 1;
irq.high &= ~EXT_IRQ;
return;
}
}
}
void extcl_cpu_wr_mem_Irem_H3000(WORD address, BYTE value) {
switch (address & 0xF000) {
case 0x8000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
map_prg_rom_8k_update();
break;
case 0x9000: {
switch (address & 0x0007) {
case 1:
if (value & 0x80) {
mirroring_H();
} else {
mirroring_V();
}
break;
case 3:
irem_H3000.enable = value & 0x80;
irq.high &= ~EXT_IRQ;
break;
case 4:
irem_H3000.count = irem_H3000.reload;
irq.high &= ~EXT_IRQ;
break;
case 5:
irem_H3000.reload = (irem_H3000.reload & 0x00FF) | (value << 8);
break;
case 6:
irem_H3000.reload = (irem_H3000.reload & 0xFF00) | value;
break;
}
break;
}
case 0xB000:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10);
break;
case 0xA000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 0xC000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 2, value);
map_prg_rom_8k_update();
break;
}
}
void extcl_cpu_wr_mem_233(WORD address, BYTE value) {
BYTE save = value;
value &= 0x1F;
if (save & 0x20) {
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
} else {
value >>= 1;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
map_prg_rom_8k_update();
switch ((save & 0xC0) >> 6) {
case 0:
mirroring_SCR0x3_SCR1x1();
break;
case 1:
mirroring_V();
break;
case 2:
mirroring_H();
break;
case 3:
mirroring_SCR1();
break;
}
}
void extcl_cpu_wr_mem_EH8813A(WORD address, BYTE value) {
if ((eh88131a.address & 0x100) == 0) {
DBWORD bank;
eh88131a.address = address & 0x01FF;
value &= 0x0F;
control_bank(info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
value = eh88131a.address & 0x07;
if (eh88131a.address & 0x80) {
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
} else {
value >>= 1;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_200(WORD address, BYTE value) {
BYTE save = (address & 0xFF);
DBWORD bank;
value = save;
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
map_prg_rom_8k_update();
value = save;
control_bank(info.chr.rom.max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
if (address & 0x0008) {
mirroring_H();
} else {
mirroring_V();
}
}
void map_init_AC08(void) {
EXTCL_CPU_WR_MEM(AC08);
EXTCL_CPU_RD_MEM(AC08);
EXTCL_SAVE_MAPPER(AC08);
mapper.internal_struct[0] = (BYTE *) &ac08;
mapper.internal_struct_size[0] = sizeof(ac08);
ac08.reg = 0;
extcl_cpu_wr_mem_AC08(0x8000, 0);
{
BYTE base, value;
base = 1;
_control_bank(base, info.prg.max_chips)
value = 0;
control_bank(info.prg.rom[base].max.banks_32k)
map_prg_rom_8k_chip(4, 0, value, base);
map_prg_rom_8k_update();
}
info.mapper.extend_wr = TRUE;
}
void extcl_cpu_wr_mem_Irem_G101(WORD address, BYTE value) {
if (address >= 0xC000) {
return;
}
switch (address & 0xF000) {
case 0x8000:
irem_G101.prg_reg = value;
irem_G101_prg_rom_update();
break;
case 0x9000:
if (info.mapper.submapper != G101B) {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
}
irem_G101.prg_mode = value & 0x02;
value = irem_G101.prg_reg;
irem_G101_prg_rom_update();
break;
case 0xA000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 0xB000:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10);
break;
}
}
static void INLINE sl1632_update(void) {
BYTE i, value;
value = sl1632.prg_map[0];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
value = sl1632.prg_map[1];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
value = 0xFE;
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 2, value);
value = 0xFF;
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 3, value);
map_prg_rom_8k_update();
for (i = 0; i < 8; i++) {
value = sl1632.chr_map[i];
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[i] = chr_chip_byte_pnt(0, value << 10);
}
sl1632_mirroring(sl1632.mirroring)
}
void extcl_cpu_wr_mem_74x161x161x32(WORD address, BYTE value) {
/* bus conflict */
const BYTE save = value &= prg_rom_rd(address);
DBWORD bank;
if (type == IC74X161X161X32B) {
if (value & 0x80) {
mirroring_SCR1();
} else {
mirroring_SCR0();
}
}
control_bank_with_AND(0x0F, info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
value = save >> 4;
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Hen_xjzb(WORD address, BYTE value) {
if ((address < 0x5000) || (address > 0x5FFF)) {
return;
}
value >>= 1;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_BMC70IN1(WORD address, BYTE value) {
if (address & 0x4000) {
bmc70in1.reg[0] = address & 0x30;
bmc70in1.reg[1] = address & 0x07;
} else {
if (address & 0x20) {
mirroring_H();
} else {
mirroring_V();
}
if (bmc70in1_type == BMC70IN1B) {
bmc70in1.reg[2] = (address & 0x03) << 3;
} else {
DBWORD bank;
value = address & 0x07;
control_bank(info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
}
switch (bmc70in1.reg[0]) {
case 0x00:
case 0x10:
value = bmc70in1.reg[2] | bmc70in1.reg[1];
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
value = bmc70in1.reg[2] | 0x07;
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 2, value);
break;
case 0x20:
value = (bmc70in1.reg[2] | bmc70in1.reg[1]) >> 1;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
break;
case 0x30:
value = bmc70in1.reg[2] | bmc70in1.reg[1];
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
break;
}
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Bandai_161x02x74(WORD address, BYTE value) {
/* bus conflict */
const BYTE save = value &= prg_rom_rd(address);
DBWORD bank;
control_bank_with_AND(0x03, info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
b161x02x74_chr_4k_update();
}
void extcl_cpu_wr_mem_Sachen_sa0037(WORD address, BYTE value) {
/* bus conflict */
const BYTE save = value &= prg_rom_rd(address);
DBWORD bank;
if (info.prg.rom.max.banks_32k != 0xFFFF) {
value >>= 3;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = save;
}
void extcl_cpu_wr_mem_Bandai_FCGX(WORD address, BYTE value) {
if (address < 0x6000) {
return;
}
if (!info.prg.ram.banks_8k_plus) {
address |= 0x8000;
}
switch (address & 0x800F) {
case 0x8000:
case 0x8001:
case 0x8002:
case 0x8003:
case 0x8004:
case 0x8005:
case 0x8006:
case 0x8007: {
const BYTE slot = address & 0x000F;
if (info.prg.rom[0].banks_16k >= 32) {
BYTE i;
FCGX.reg[slot] = value;
value = 0;
for (i = 0; i < 8; i++) {
value |= (FCGX.reg[i] << 4) & 0x10;
}
value |= ((mapper.rom_map_to[0] >> 1) & 0x0F);
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
value |= 0x0F;
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 2, value);
map_prg_rom_8k_update();
value = FCGX.reg[slot];
}
if (type == DATACH) {
datach_set_scl((value << 2) & 0x20);
}
if (!mapper.write_vram) {
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[slot] = chr_chip_byte_pnt(0, value << 10);
}
return;
}
case 0x8008:
if (info.prg.rom[0].banks_16k >= 32) {
value = ((mapper.rom_map_to[0] >> 1) & 0x10) | (value & 0x0F);
}
void extcl_cpu_wr_mem_242(WORD address, BYTE value) {
if (address & 0x0002) {
mirroring_H();
} else {
mirroring_V();
}
value = (address & 0x0078) >> 3;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Hen_177(WORD address, BYTE value) {
if (type != HEN_FANKONG) {
if (value & 0x20) {
mirroring_H();
} else {
mirroring_V();
}
}
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Ntdec_asder(WORD address, BYTE value) {
switch (address & 0xE001) {
case 0x8000:
asder.address = value & 0x07;
return;
case 0xA000: {
switch (asder.address) {
case 0:
case 1:
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, asder.address, value);
map_prg_rom_8k_update();
return;
case 2:
case 3:
asder.reg[asder.address] = value >> 1;
break;
case 4:
case 5:
case 6:
case 7:
asder.reg[asder.address] = value;
break;
}
break;
}
case 0xC000:
asder.reg[0] = value;
break;
case 0xE000:
asder.reg[1] = value;
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
break;
}
{
DBWORD bank;
const WORD chr_high = (asder.reg[1] & 0x02) ? asder.reg[0] : 0;
WORD new_value;
asder_chr_2k_update(5, 2, 0, 1);
asder_chr_2k_update(4, 3, 2, 3);
asder_chr_1k_update(4, 4);
asder_chr_1k_update(3, 5);
asder_chr_1k_update(2, 6);
asder_chr_1k_update(1, 7);
}
}
void extcl_cpu_wr_mem_Irem_LROG017(WORD address, BYTE value) {
/* bus conflict */
const BYTE save = value &= prg_rom_rd(address);
DBWORD bank;
control_bank_with_AND(0x0F, info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = save >> 4;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
}
void extcl_cpu_wr_mem_AxROM(WORD address, BYTE value) {
/* bus conflict */
if (info.mapper.submapper == AMROM) {
value &= prg_rom_rd(address);
}
if (value & 0x10) {
mirroring_SCR0();
} else {
mirroring_SCR1();
}
control_bank_with_AND(0x0F, info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Ntdec_fhero(WORD address, BYTE value) {
if ((address < 0x6000) || (address > 0x7FFF)) {
return;
}
switch (address & 0x0003) {
case 0: {
DBWORD bank;
value >>= 2;
control_bank(info.chr.rom.max.banks_4k)
bank = value << 12;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
return;
}
case 1: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
}
case 2: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400);
return;
}
case 3:
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, 0, value);
map_prg_rom_8k_update();
return;
}
}
void extcl_cpu_wr_mem_NovelDiamond(WORD address, BYTE value) {
DBWORD bank;
value = address & 0x03;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = address & 0x07;
control_bank(info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
void extcl_cpu_wr_mem_Magic(WORD address, BYTE value) {
const BYTE save = value;
DBWORD bank;
value >>= 1;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = save;
control_bank(info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
static void INLINE sl1632_update_mmc3(void) {
WORD value;
value = sl1632.mmc3.prg_map[0];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
value = sl1632.mmc3.prg_map[1];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
value = sl1632.mmc3.prg_map[2];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 2, value);
value = sl1632.mmc3.prg_map[3];
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 3, value);
map_prg_rom_8k_update();
sl1632_update_chr_mmc3();
sl1632_mirroring(sl1632.mmc3.mirroring)
}
void extcl_cpu_wr_mem_VRC3(WORD address, BYTE value) {
switch (address & 0xF000) {
case 0x8000:
vrc3.reload = (vrc3.reload & 0xFFF0) | (value & 0x0F);
return;
case 0x9000:
vrc3.reload = (vrc3.reload & 0xFF0F) | ((value & 0x0F) << 4);
return;
case 0xA000:
vrc3.reload = (vrc3.reload & 0xF0FF) | ((value & 0x0F) << 8);
return;
case 0xB000:
vrc3.reload = (vrc3.reload & 0x0FFF) | ((value & 0x0F) << 12);
return;
case 0xC000:
vrc3.acknowledge = value & 0x01;
vrc3.enabled = value & 0x02;
vrc3.mode = value & 0x04;
vrc3.mask = 0xFFFF;
if (vrc3.mode) {
vrc3.mask = 0x00FF;
}
if (vrc3.enabled) {
vrc3.count = vrc3.reload;
}
irq.high &= ~EXT_IRQ;
return;
case 0xD000:
vrc3.enabled = vrc3.acknowledge;
irq.high &= ~EXT_IRQ;
return;
case 0xF000:
control_bank_with_AND(0x0F, info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k_update();
return;
default:
return;
}
}
void extcl_cpu_wr_mem_240(WORD address, BYTE value) {
if ((address >= 0x4020) && (address < 0x6000)) {
DBWORD bank;
BYTE save = value;
value >>= 4;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = save;
control_bank(info.chr.rom.max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
void extcl_cpu_wr_mem_SC_127(WORD address, BYTE value) {
switch (address) {
case 0x8000:
case 0x8001:
case 0x8002:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, address & 0x03, value);
map_prg_rom_8k_update();
return;
case 0x9000:
case 0x9001:
case 0x9002:
case 0x9003:
case 0x9004:
case 0x9005:
case 0x9006:
case 0x9007:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x07] = chr_chip_byte_pnt(0, value << 10);
return;
case 0xC002:
sc127.irq.active = 0;
irq.high &= ~EXT_IRQ;
return;
case 0xC003:
sc127.irq.active = 1;
return;
case 0xC005:
sc127.irq.count = value;
return;
case 0xD001:
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
return;
}
}
void extcl_cpu_wr_mem_GxROM(WORD address, BYTE value) {
/* bus conflict */
BYTE save = value &= prg_rom_rd(address);
DBWORD bank;
value >>= 4;
control_bank_with_AND(0x03, info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
value = save;
control_bank_with_AND(0x03, info.chr.rom.max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
void extcl_cpu_wr_mem_186(WORD address, BYTE value) {
if ((address < 0x4200) || (address > 0x4EFF)) {
return;
}
if (address > 0x43FF) {
prg.ram.data[address & 0x0BFF] = value;
return;
}
switch (address & 0x0001) {
case 0x0000:
value >>= 6;
control_bank(info.prg.rom.max.banks_8k)
m186.prg_ram_bank2 = prg_chip_byte_pnt(0, value << 13);
return;
case 0x0001:
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k_update();
return;
}
}
void extcl_cpu_wr_mem_182(WORD address, BYTE value) {
switch (address & 0xE001) {
case 0x8001:
extcl_cpu_wr_mem_MMC3(0xA000, value);
return;
case 0xA000:
extcl_cpu_wr_mem_MMC3(0x8000, value);
return;
case 0xC000: {
switch (mmc3.bank_to_update) {
case 0: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
chr.bank_1k[mmc3.chr_rom_cfg] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[mmc3.chr_rom_cfg | 0x01] = chr_chip_byte_pnt(0, bank | 0x0400);
break;
}
case 1:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x01] = chr_chip_byte_pnt(0, value << 10);
break;
case 2: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
chr.bank_1k[mmc3.chr_rom_cfg | 0x02] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[mmc3.chr_rom_cfg | 0x03] = chr_chip_byte_pnt(0, bank | 0x0400);
break;
}
case 3:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x03] = chr_chip_byte_pnt(0, value << 10);
break;
case 4:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, mmc3.prg_rom_cfg, value);
map_prg_rom_8k_update();
break;
case 5:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 6:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[mmc3.chr_rom_cfg ^ 0x04] = chr_chip_byte_pnt(0, value << 10);
break;
case 7:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x02] = chr_chip_byte_pnt(0, value << 10);
break;
}
return;
}
case 0xC001:
irqA12.latch = value;
irqA12.reload = TRUE;
irqA12.counter = 0;
return;
case 0xE000:
case 0xE001:
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
}
