/*
* This interrupt ISR maybe one of several registered via fpgaIntConnect() the the FPGA
* external interrupt.
* There is a Base ISR that handles reading the interrupt status register
* it passes this as the 1st argument to all the register ISRs, the 2nd argument
* the the argument specified in the fpgaInitConnect call
* As such the 1st thing it checks is if and uarts need to be serviced, if not it returns
* immediately so the next ISR on the chain can be called.
* The base ISR clear the interrupts, Do NOT clear them in register ISRs
* FPGA serial port ISR, all serialport plus all the other interrupt are generated
* via the one 405 external interrupt IRQ0.
* This routine decide which if any serial ports need servicing add call the Sio
* ISR to handle that serial port channel.
*
* Author: greg Brissey 5/7/04
*/
void masterFpgaNs16550Isr(int pendingItrs, int dummy)
{
extern void ns16550Int ( NS16550_CHAN * pChan); /* pointer to channel */
int uarts;
/* its passed so don't read it */
/* uarts = get_field(MASTER,uart_int_status); */
uarts = mask_value(MASTER,uart_int_status,pendingItrs);
// logMsg("fpga serial ISR: pending: 0x%lx, uarts: 0x%x\n",pendingItrs,uarts,3,4,5,6);
/* No UARTs need servicing then just return */
if (uarts == 0)
return;
if (uarts & 1)
{
/* logMsg("ISR: chan 0\n"); */
ns16550Int(ns16550Chans[0]);
/* fpgaClearUartInt(0); */
}
if (uarts & 2)
{
/* logMsg("ISR: chan 1\n"); */
ns16550Int(ns16550Chans[1]);
/* fpgaClearUartInt(1); */
}
if (uarts & 4)
{
/* logMsg("ISR: chan 2\n"); */
ns16550Int(ns16550Chans[2]);
/* fpgaClearUartInt(2); */
}
if (uarts & 8)
{
/* logMsg("ISR: chan 3\n"); */
ns16550Int(ns16550Chans[3]);
/* fpgaClearUartInt(3); */
}
return;
}
int main()
{
printf("***** build time %s %s %d %s *****\n", __TIME__,__DATE__,__GNUC__,__VERSION__);
test_equal(mask_value(0xf0, BIT(0)), 0);
test_equal(mask_value(0xf0, BIT(1)), 0);
test_equal(mask_value(0xf0, BIT(2)), 0);
test_equal(mask_value(0xf0, BIT(3)), 0);
test_equal(mask_value(0xf0, BIT(4)), 1);
test_equal(mask_value(0xf0, BIT(5)), 1);
test_equal(mask_value(0xf0, BIT(6)), 1);
test_equal(mask_value(0xf0, BIT(7)), 1);
test_equal(mask_value(0xf0, BIT(2) | BIT(3)), 0);
test_equal(mask_value(0xf0, BIT(3) | BIT(4)), 2);
test_equal(mask_value(0xf0, BIT(4) | BIT(5)), 3);
test_equal(mask_value(0xf0, BIT(6) | BIT(7)), 3);
test_equal(BIT_MASK(3, 5), 0x38);
test_equal(BIT_MASK(3, 6), 0x78);
test_equal(BIT_MASK(4, 7), 0xf0);
test_equal(mask_value(0xf0, BIT_MASK(2, 3)), 0);
test_equal(mask_value(0xf0, BIT_MASK(3, 4)), 2);
test_equal(mask_value(0xf0, BIT_MASK(4, 5)), 3);
test_equal(mask_value(0xf0, BIT_MASK(6, 7)), 3);
test_equal(mask_value(0xf0, BIT_MASK(3, 5)), 6);
test_equal(mask_value(0xf0, BIT_MASK(3, 6)), 0xe);
test_equal(mask_value(0xf0, BIT_MASK(4, 7)), 0xf);
test_ffs();
return 0;
}
bool is_valid()const { return (ip_value() && mask_value() && mask.bits() >= MINBANMASK); }
