static int mcp_sa11x0_probe(struct platform_device *pdev)
{
struct mcp_plat_data *data = pdev->dev.platform_data;
struct mcp *mcp;
int ret;
if (!data)
return -ENODEV;
if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp"))
return -EBUSY;
mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
if (!mcp) {
ret = -ENOMEM;
goto release;
}
mcp->owner = THIS_MODULE;
mcp->ops = &mcp_sa11x0;
mcp->sclk_rate = data->sclk_rate;
mcp->dma_audio_rd = DMA_Ser4MCP0Rd;
mcp->dma_audio_wr = DMA_Ser4MCP0Wr;
mcp->dma_telco_rd = DMA_Ser4MCP1Rd;
mcp->dma_telco_wr = DMA_Ser4MCP1Wr;
platform_set_drvdata(pdev, mcp);
if (machine_is_assabet()) {
ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
}
PPDR &= ~PPC_RXD4;
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PSDR |= PPC_RXD4;
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
Ser4MCSR = -1;
Ser4MCCR1 = data->mccr1;
Ser4MCCR0 = data->mccr0 | 0x7f7f;
mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
mcp->sclk_rate;
ret = mcp_host_register(mcp);
if (ret == 0)
goto out;
release:
release_mem_region(0x80060000, 0x60);
platform_set_drvdata(pdev, NULL);
out:
return ret;
}
static int mcp_sa11x0_probe(struct platform_device *pdev)
{
struct mcp_plat_data *data = pdev->dev.platform_data;
struct mcp *mcp;
int ret;
if (!data)
return -ENODEV;
if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp"))
return -EBUSY;
mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
if (!mcp) {
ret = -ENOMEM;
goto release;
}
mcp->owner = THIS_MODULE;
mcp->ops = &mcp_sa11x0;
mcp->sclk_rate = data->sclk_rate;
mcp->dma_audio_rd = DMA_Ser4MCP0Rd;
mcp->dma_audio_wr = DMA_Ser4MCP0Wr;
mcp->dma_telco_rd = DMA_Ser4MCP1Rd;
mcp->dma_telco_wr = DMA_Ser4MCP1Wr;
mcp->gpio_base = data->gpio_base;
platform_set_drvdata(pdev, mcp);
if (machine_is_assabet()) {
ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
}
/*
* Setup the PPC unit correctly.
*/
PPDR &= ~PPC_RXD4;
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PSDR |= PPC_RXD4;
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
/*
* Initialise device. Note that we initially
* set the sampling rate to minimum.
*/
Ser4MCSR = -1;
Ser4MCCR1 = data->mccr1;
Ser4MCCR0 = data->mccr0 | 0x7f7f;
/*
* Calculate the read/write timeout (us) from the bit clock
* rate. This is the period for 3 64-bit frames. Always
* round this time up.
*/
mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
mcp->sclk_rate;
ret = mcp_host_register(mcp);
if (ret == 0)
goto out;
release:
release_mem_region(0x80060000, 0x60);
platform_set_drvdata(pdev, NULL);
out:
return ret;
}
static int mcp_sa11x0_probe(struct platform_device *pdev)
{
struct mcp_plat_data *data = pdev->dev.platform_data;
struct mcp *mcp;
int ret;
struct mcp_sa11x0 *priv;
struct resource *res_mem0, *res_mem1;
u32 size0, size1;
if (!data)
return -ENODEV;
if (!data->codec)
return -ENODEV;
res_mem0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res_mem0)
return -ENODEV;
size0 = res_mem0->end - res_mem0->start + 1;
res_mem1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res_mem1)
return -ENODEV;
size1 = res_mem1->end - res_mem1->start + 1;
if (!request_mem_region(res_mem0->start, size0, "sa11x0-mcp"))
return -EBUSY;
if (!request_mem_region(res_mem1->start, size1, "sa11x0-mcp")) {
ret = -EBUSY;
goto release;
}
mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
if (!mcp) {
ret = -ENOMEM;
goto release2;
}
priv = priv(mcp);
mcp->owner = THIS_MODULE;
mcp->ops = &mcp_sa11x0;
mcp->sclk_rate = data->sclk_rate;
mcp->dma_audio_rd = DDAR_DevAdd(res_mem0->start + MCDR0)
+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
mcp->dma_audio_wr = DDAR_DevAdd(res_mem0->start + MCDR0)
+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
mcp->dma_telco_rd = DDAR_DevAdd(res_mem0->start + MCDR1)
+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
mcp->dma_telco_wr = DDAR_DevAdd(res_mem0->start + MCDR1)
+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
mcp->codec = data->codec;
platform_set_drvdata(pdev, mcp);
/*
* Initialise device. Note that we initially
* set the sampling rate to minimum.
*/
priv->mccr0_base = ioremap(res_mem0->start, size0);
priv->mccr1_base = ioremap(res_mem1->start, size1);
__raw_writel(-1, priv->mccr0_base + MCSR);
priv->mccr1 = data->mccr1;
priv->mccr0 = data->mccr0 | 0x7f7f;
__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
__raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);
/*
* Calculate the read/write timeout (us) from the bit clock
* rate. This is the period for 3 64-bit frames. Always
* round this time up.
*/
mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
mcp->sclk_rate;
ret = mcp_host_register(mcp, data->codec_pdata);
if (ret == 0)
goto out;
release2:
release_mem_region(res_mem1->start, size1);
release:
release_mem_region(res_mem0->start, size0);
platform_set_drvdata(pdev, NULL);
out:
return ret;
}