void fimc_isp_irq_handler(struct fimc_is *is)
{
is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
fimc_isp_video_irq_handler(is);
wake_up(&is->irq_queue);
}
void fimc_isp_irq_handler(struct fimc_is *is)
{
is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
/* TODO: Complete ISP DMA interrupt handler */
wake_up(&is->irq_queue);
}
int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)
{
unsigned int timeout = 2000;
u32 cfg, status;
cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
status = INTMSR0_GET_INTMSD(0, cfg);
while (status) {
cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
status = INTMSR0_GET_INTMSD(0, cfg);
if (timeout == 0) {
dev_warn(&is->pdev->dev, "%s timeout\n",
__func__);
return -ETIME;
}
timeout--;
udelay(1);
}
return 0;
}
int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)
{
int i;
if (num_args > FIMC_IS_MAX_PARAMS)
return -EINVAL;
is->i2h_cmd.num_args = num_args;
for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) {
if (i < num_args)
is->i2h_cmd.args[i] = mcuctl_read(is,
MCUCTL_REG_ISSR(12 + i));
else
is->i2h_cmd.args[i] = 0;
}
return 0;
}
static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
{
struct fimc_is *is = priv;
unsigned long flags;
u32 status;
spin_lock_irqsave(&is->slock, flags);
status = mcuctl_read(is, MCUCTL_REG_INTSR1);
if (status & (1UL << FIMC_IS_INT_GENERAL))
fimc_is_general_irq_handler(is);
if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
fimc_isp_irq_handler(is);
spin_unlock_irqrestore(&is->slock, flags);
return IRQ_HANDLED;
}
void fimc_is_fw_clear_irq2(struct fimc_is *is)
{
u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);
mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);
}
/* General IS interrupt handler */
static void fimc_is_general_irq_handler(struct fimc_is *is)
{
is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
switch (is->i2h_cmd.cmd) {
case IHC_GET_SENSOR_NUM:
fimc_is_hw_get_params(is, 1);
fimc_is_hw_wait_intmsr0_intmsd0(is);
fimc_is_hw_set_sensor_num(is);
pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
break;
case IHC_SET_FACE_MARK:
case IHC_FRAME_DONE:
fimc_is_hw_get_params(is, 2);
break;
case IHC_SET_SHOT_MARK:
case IHC_AA_DONE:
case IH_REPLY_DONE:
fimc_is_hw_get_params(is, 3);
break;
case IH_REPLY_NOT_DONE:
fimc_is_hw_get_params(is, 4);
break;
case IHC_NOT_READY:
break;
default:
pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
}
fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
switch (is->i2h_cmd.cmd) {
case IHC_GET_SENSOR_NUM:
fimc_is_hw_set_intgr0_gd0(is);
set_bit(IS_ST_A5_PWR_ON, &is->state);
break;
case IHC_SET_SHOT_MARK:
break;
case IHC_SET_FACE_MARK:
is->fd_header.count = is->i2h_cmd.args[0];
is->fd_header.index = is->i2h_cmd.args[1];
is->fd_header.offset = 0;
break;
case IHC_FRAME_DONE:
break;
case IHC_AA_DONE:
pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
break;
case IH_REPLY_DONE:
pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
switch (is->i2h_cmd.args[0]) {
case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
/* Get CAC margin */
set_bit(IS_ST_CHANGE_MODE, &is->state);
is->isp.cac_margin_x = is->i2h_cmd.args[1];
is->isp.cac_margin_y = is->i2h_cmd.args[2];
pr_debug("CAC margin (x,y): (%d,%d)\n",
is->isp.cac_margin_x, is->isp.cac_margin_y);
break;
case HIC_STREAM_ON:
clear_bit(IS_ST_STREAM_OFF, &is->state);
set_bit(IS_ST_STREAM_ON, &is->state);
break;
case HIC_STREAM_OFF:
clear_bit(IS_ST_STREAM_ON, &is->state);
set_bit(IS_ST_STREAM_OFF, &is->state);
break;
case HIC_SET_PARAMETER:
is->config[is->config_index].p_region_index1 = 0;
is->config[is->config_index].p_region_index2 = 0;
set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
pr_debug("HIC_SET_PARAMETER\n");
break;
case HIC_GET_PARAMETER:
break;
case HIC_SET_TUNE:
break;
case HIC_GET_STATUS:
break;
case HIC_OPEN_SENSOR:
set_bit(IS_ST_OPEN_SENSOR, &is->state);
pr_debug("data lanes: %d, settle line: %d\n",
is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
break;
case HIC_CLOSE_SENSOR:
clear_bit(IS_ST_OPEN_SENSOR, &is->state);
is->sensor_index = 0;
break;
case HIC_MSG_TEST:
pr_debug("config MSG level completed\n");
break;
case HIC_POWER_DOWN:
clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
break;
case HIC_GET_SET_FILE_ADDR:
is->setfile.base = is->i2h_cmd.args[1];
set_bit(IS_ST_SETFILE_LOADED, &is->state);
break;
case HIC_LOAD_SET_FILE:
set_bit(IS_ST_SETFILE_LOADED, &is->state);
break;
}
break;
case IH_REPLY_NOT_DONE:
pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
is->i2h_cmd.args[1],
fimc_is_strerr(is->i2h_cmd.args[1]));
if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
pr_err("IS_ERROR_TIME_OUT\n");
switch (is->i2h_cmd.args[1]) {
case IS_ERROR_SET_PARAMETER:
fimc_is_mem_barrier();
}
switch (is->i2h_cmd.args[0]) {
case HIC_SET_PARAMETER:
is->config[is->config_index].p_region_index1 = 0;
is->config[is->config_index].p_region_index2 = 0;
set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
break;
}
break;
case IHC_NOT_READY:
pr_err("IS control sequence error: Not Ready\n");
break;
}
wake_up(&is->irq_queue);
}
