void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on) {
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 1);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
static void mdp4_dsi_cmd_overlay_nolock( struct msm_fb_data_type *mfd )
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mdp_clk_ctrl(1);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_dsi_cmd_busy();
mdp4_overlay_mdp_perf_upd(mfd, 0);
mdp_clk_ctrl(0);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
long long xx;
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
vctrl->clk_control = 0;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit();
mdp4_dsi_cmd_wait4vsync(0, &xx);
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
vctrl->clk_control = 1;
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
vctrl = &vsync_ctrl_db[cndx];
atomic_inc(&in_drawing);
if (!mfd->panel_power_on) {
atomic_dec(&in_drawing);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
atomic_dec(&in_drawing);
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (!vctrl->clk_enabled) {
atomic_dec(&in_drawing);
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->expire_tick) {
/*
* in the middle of shutting clocks down
* delay to allow pan display to go through
*/
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
mdp4_dsi_cmd_pipe_commit();
mutex_unlock(&mfd->dma->ov_mutex);
/* mdp4_overlay_mdp_perf_upd(mfd, 0); */
atomic_dec(&in_drawing);
}
void mdp4_dsi_refresh_screen_at_once( struct msm_fb_data_type *mfd )
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
DISP_LOCAL_LOG_EMERG("DISP %s S\n",__func__);
if( mfd == NULL ){
return;
}
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mdp_clk_ctrl(1);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_screen_at_once_flag = 1;
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_dsi_screen_at_once_flag = 0;
mdp4_dsi_cmd_busy();
mdp4_overlay_mdp_perf_upd(mfd, 0);
mdp_clk_ctrl(0);
DISP_LOCAL_LOG_EMERG("DISP %s E\n",__func__);
return;
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on) {
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
/* OPPO 2013-10-19 gousj Modify begin for WFD crash */
#ifndef CONFIG_VENDOR_EDIT
mdp4_dsi_cmd_pipe_commit(cndx, 1);
#else
mdp4_dsi_cmd_pipe_commit(cndx, 0);
#endif
/* OPPO 2013-10-19 gousj Modify end */
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_overlay_update_dsi_cmd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
uint8 *src;
int ptype;
struct mdp4_overlay_pipe *pipe;
struct msm_fb_data_type *tmp_dsi_mfd;
int bpp;
int ret;
if (mfd->key != MFD_KEY)
return;
tmp_dsi_mfd = dsi_mfd;
dsi_mfd = mfd; /* keep it */
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (unlikely(dsi_pipe == NULL)) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (unlikely(ptype < 0)) {
printk(KERN_ERR "%s: format2type failed\n", __func__);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
dsi_mfd = tmp_dsi_mfd;
return;
}
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
if (unlikely(pipe == NULL)) {
printk(KERN_ERR "%s: pipe_alloc failed\n", __func__);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
dsi_mfd = tmp_dsi_mfd;
return;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_CMD);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
init_timer(&dsi_clock_timer);
dsi_clock_timer.function = dsi_clock_tout;
dsi_clock_timer.data = (unsigned long) mfd;;
dsi_clock_timer.expires = 0xffffffff;
add_timer(&dsi_clock_timer);
tout_expired = jiffies;
dsi_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = dsi_pipe;
}
/*
* configure dsi stream id
* dma_p = 0, dma_s = 1
*/
MDP_OUTP(MDP_BASE + 0x000a0, 0x10);
/* disable dsi trigger */
MDP_OUTP(MDP_BASE + 0x000a4, 0x00);
/* whole screen for base layer */
src = (uint8 *) iBuf->buf;
{
struct fb_info *fbi;
fbi = mfd->fbi;
if (pipe->is_3d) {
bpp = fbi->var.bits_per_pixel / 8;
pipe->src_height = pipe->src_height_3d;
pipe->src_width = pipe->src_width_3d;
pipe->src_h = pipe->src_height_3d;
pipe->src_w = pipe->src_width_3d;
pipe->dst_h = pipe->src_height_3d;
pipe->dst_w = pipe->src_width_3d;
pipe->srcp0_ystride = msm_fb_line_length(0,
pipe->src_width, bpp);
} else {
/* 2D */
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
}
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32)src;
}
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
mdp4_mipi_vsync_enable(mfd, pipe, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
wmb();
}
void mdp4_overlay_update_dsi_cmd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
uint8 *src;
int ptype;
struct mdp4_overlay_pipe *pipe;
int bpp;
int ret;
if (mfd->key != MFD_KEY)
return;
dsi_mfd = mfd; /* keep it */
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (dsi_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
if (pipe == NULL)
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_CMD);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
#ifdef DSI_CLK_CTRL
init_timer(&dsi_clock_timer);
dsi_clock_timer.function = dsi_clock_tout;
dsi_clock_timer.data = (unsigned long) mfd;;
dsi_clock_timer.expires = HZ;
#endif
dsi_pipe = pipe; /* keep it */
#ifdef OVERLAY_BLT_EMBEDDED
{
char *src;
struct fb_info *fbi;
int bpp, off;
fbi = mfd->fbi;
bpp = fbi->var.bits_per_pixel / 8;
src = (uint8 *) iBuf->buf;
pipe->blt_base = (ulong) iBuf->buf;
off = ALIGN(fbi->var.xres, 32) * fbi->var.yres
* bpp * 2;
off += (1920 * 1080 * 2 * 1); /* hdmi */
pipe->blt_base += off;
pr_info("%s: base=%x offset=%x\n",
__func__, (int) pipe->blt_base, (int)off);
}
#endif
/*
* configure dsi stream id
* dma_p = 0, dma_s = 1
*/
MDP_OUTP(MDP_BASE + 0x000a0, 0x10);
/* enable dsi trigger on dma_p */
MDP_OUTP(MDP_BASE + 0x000a4, 0x01);
} else {
pipe = dsi_pipe;
}
/* whole screen for base layer */
src = (uint8 *) iBuf->buf;
{
struct fb_info *fbi;
fbi = mfd->fbi;
if (pipe->is_3d) {
bpp = fbi->var.bits_per_pixel / 8;
pipe->src_height = pipe->src_height_3d;
pipe->src_width = pipe->src_width_3d;
pipe->src_h = pipe->src_height_3d;
pipe->src_w = pipe->src_width_3d;
pipe->dst_h = pipe->src_height_3d;
pipe->dst_w = pipe->src_width_3d;
pipe->srcp0_ystride = msm_fb_line_length(0,
pipe->src_width, bpp);
} else {
/* 2D */
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
}
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32)src;
}
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
mdp4_mipi_vsync_enable(mfd, pipe, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
wmb();
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int clk_set_on = 0;
#if defined(CONFIG_MACH_JAGUAR)
static int logo;
#endif
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) || \
defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT)
if (!is_lcd_connected)
return;
#endif
mutex_lock(&vctrl->update_lock);
if (atomic_read(&vctrl->suspend)) {
#if defined(CONFIG_MACH_JAGUAR)
if (!logo || poweroff_charging ) {
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR,
MDP_PRIM_RDPTR_TERM);
logo = 1;
} else {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
#else
mutex_unlock(&vctrl->update_lock);
pr_err("%s: suspended, no more pan display\n", __func__);
return;
#endif
}
spin_lock_irqsave(&vctrl->spin_lock, flags);
vctrl->clk_control = 0;
vctrl->pan_display++;
if (!vctrl->clk_enabled) {
clk_set_on = 1;
vctrl->clk_enabled = 1;
}
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (clk_set_on) {
pr_err("%s: warning, clock off while pan display\n", __func__);
pr_debug("%s: SET_CLK_ON\n", __func__);
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vsync_irq_enable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM);
}
mutex_unlock(&vctrl->update_lock);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mutex_lock(&mfd->dma->ov_mutex);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_dsi_cmd_pipe_commit(cndx, 0);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
static void mdp4_overlay_update_dsi_cmd(struct msm_fb_data_type *mfd)
{
int ptype;
struct mdp4_overlay_pipe *pipe;
int ret;
int cndx = 0;
struct vsycn_ctrl *vctrl;
if (mfd->key != MFD_KEY)
return;
vctrl = &vsync_ctrl_db[cndx];
if (vctrl->base_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
return;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_CMD);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
vctrl->base_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
} else {
pipe = vctrl->base_pipe;
}
/* TE enabled */
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mdp4_calc_blt_mdp_bw(mfd, pipe);
MDP_OUTP(MDP_BASE + 0x021c, 10); /* read pointer */
/*
* configure dsi stream id
* dma_p = 0, dma_s = 1
*/
MDP_OUTP(MDP_BASE + 0x000a0, 0x10);
/* disable dsi trigger */
MDP_OUTP(MDP_BASE + 0x000a4, 0x00);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_overlay_rgb_setup(pipe);
mdp4_overlay_reg_flush(pipe, 1);
mdp4_mixer_stage_up(pipe, 0);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
wmb();
}
void mdp4_dsi_cmd_3d(struct msm_fb_data_type *mfd, struct msmfb_overlay_3d *r3d)
{
MDPIBUF *iBuf = &mfd->ibuf;
struct fb_info *fbi;
struct mdp4_overlay_pipe *pipe;
int bpp;
uint8 *src = NULL;
if (r3d->is_3d == PADDING_ENABLE || r3d->is_3d == PADDING_DISABLE) {
mfd->enable_uipadding = r3d->is_3d;
if (r3d->is_3d == PADDING_DISABLE)
mdp4_overlay_handle_padding(mfd, false);
return;
}
if (dsi_pipe == NULL)
return;
PR_DISP_INFO("%s(%d) is3d %d pid=%d\n", __func__, __LINE__, r3d->is_3d, current->pid);
dsi_pipe->is_3d = r3d->is_3d;
dsi_pipe->src_height_3d = r3d->height;
dsi_pipe->src_width_3d = r3d->width;
src = (uint8 *) iBuf->buf;
pipe = dsi_pipe;
#ifdef CONFIG_FB_MSM_MIPI_DSI
if (mfd->panel_power_on)
mdp4_dsi_cmd_dma_busy_wait(mfd, pipe);
if (dsi_pipe->blt_addr)
mdp4_dsi_blt_dmap_busy_wait(mfd);
#endif
fbi = mfd->fbi;
if (pipe->is_3d) {
bpp = fbi->var.bits_per_pixel / 8;
pipe->src_height = pipe->src_height_3d;
pipe->src_width = pipe->src_width_3d;
pipe->src_h = pipe->src_height_3d;
pipe->src_w = pipe->src_width_3d;
pipe->dst_h = pipe->src_height_3d;
pipe->dst_w = pipe->src_width_3d;
pipe->srcp0_ystride = msm_fb_line_length(0, pipe->src_width, bpp);
} else {
/* 2D */
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
}
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32)src;
PR_DISP_DEBUG("%s(%d) is3d %d srcx %d srcy %d srcw %d srch %d dstx %d dsty %d dstw %d dsth %d ystride %d\n", __func__, __LINE__, pipe->is_3d,
pipe->src_x, pipe->src_y, pipe->src_w, pipe->src_h,
pipe->dst_x, pipe->dst_y, pipe->dst_w, pipe->dst_h, pipe->srcp0_ystride);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
mdp4_mipi_vsync_enable(mfd, pipe, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
wmb();
}
void mdp4_overlay_update_dsi_cmd(struct msm_fb_data_type *mfd)
{
MDPIBUF *iBuf = &mfd->ibuf;
struct fb_info *fbi;
uint8 *src;
int ptype;
struct mdp4_overlay_pipe *pipe;
int ret;
int bpp;
if (mfd->key != MFD_KEY)
return;
dsi_mfd = mfd; /* keep it */
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (dsi_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
return;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
pipe->is_3d = 0;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_CMD);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
dsi_pipe = pipe; /* keep it */
fbi = mfd->fbi;
bpp = fbi->var.bits_per_pixel / 8;
src = (uint8 *) iBuf->buf;
writeback_offset = mdp4_overlay_writeback_setup(
fbi, pipe, src, bpp);
#ifdef OVERLAY_BLT_EMBEDDED
pipe->blt_base = mfd->blt_base;
PR_DISP_INFO("%s: blt_base=%08x\n", __func__,
(uint32_t)pipe->blt_base);
#endif
/*
* configure dsi stream id
* dma_p = 0, dma_s = 1
*/
MDP_OUTP(MDP_BASE + 0x000a0, 0x10);
/* enable dsi trigger on dma_p */
MDP_OUTP(MDP_BASE + 0x000a4, 0x01);
MDP_OUTP(MDP_BASE + 0x0021c, 0x10);
} else {
pipe = dsi_pipe;
}
/* whole screen for base layer */
src = (uint8 *) iBuf->buf;
{
struct fb_info *fbi;
fbi = mfd->fbi;
if (pipe->is_3d) {
bpp = fbi->var.bits_per_pixel / 8;
pipe->src_height = pipe->src_height_3d;
pipe->src_width = pipe->src_width_3d;
pipe->src_h = pipe->src_height_3d;
pipe->src_w = pipe->src_width_3d;
pipe->dst_h = pipe->src_height_3d;
pipe->dst_w = pipe->src_width_3d;
pipe->srcp0_ystride = msm_fb_line_length(0, pipe->src_width, bpp);
} else {
/* 2D */
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
}
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_y = 0;
pipe->dst_x = 0;
pipe->srcp0_addr = (uint32)src;
}
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
mdp4_overlay_dmap_cfg(mfd, 0);
mdp4_mipi_vsync_enable(mfd, pipe, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
wmb();
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
#ifdef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
long long tick;
#endif
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on)
return;
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
return;
}
mutex_lock(&vctrl->update_lock);
if (!vctrl->clk_enabled) {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
return;
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->expire_tick) {
/*
* in the middle of shutting clocks down
* delay to allow pan display to go through
*/
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mipi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_dsi_cmd_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
#ifndef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
//mdp4_dsi_cmd_pipe_commit();
#else
mdp4_dsi_cmd_pipe_commit(cndx, 0);
#endif
mutex_unlock(&mfd->dma->ov_mutex);
#ifdef CONFIG_VENDOR_EDIT
//liuyan modify for mhl fick in playing video
mdp4_dsi_cmd_wait4vsync(cndx, &tick);
#endif
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
int mdp4_dsi_cmd_pipe_commit(int cndx, int wait)
{
int i, undx;
int mixer = 0;
struct vsycn_ctrl *vctrl;
struct vsync_update *vp;
struct mdp4_overlay_pipe *pipe;
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int need_dmap_wait = 0;
int need_ov_wait = 0;
int cnt = 0;
vctrl = &vsync_ctrl_db[0];
mutex_lock(&vctrl->update_lock);
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&vctrl->update_lock);
return 0;
}
mixer = pipe->mixer_num;
mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
/*
* allow stage_commit without pipes queued
* (vp->update_cnt == 0) to unstage pipes after
* overlay_unset
*/
vctrl->update_ndx++;
vctrl->update_ndx &= 0x01;
vp->update_cnt = 0; /* reset */
if (vctrl->blt_free) {
vctrl->blt_free--;
if (vctrl->blt_free == 0)
mdp4_free_writeback_buf(vctrl->mfd, mixer);
}
if(!mdp4_dsi_screen_at_once_flag){
if (mdp4_dsi_cmd_clk_check(vctrl) < 0) {
mdp4_dsi_cmd_pipe_clean(vp);
mutex_unlock(&vctrl->update_lock);
return 0;
}
}
mutex_unlock(&vctrl->update_lock);
/* free previous committed iommu back to pool */
mdp4_overlay_iommu_unmap_freelist(mixer);
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
/* Blt */
if (vctrl->blt_wait) {
INIT_COMPLETION(vctrl->dmap_comp);
need_dmap_wait = 1;
}
if (vctrl->ov_koff != vctrl->ov_done) {
INIT_COMPLETION(vctrl->ov_comp);
need_ov_wait = 1;
}
} else {
/* direct out */
if (vctrl->dmap_koff != vctrl->dmap_done) {
INIT_COMPLETION(vctrl->dmap_comp);
pr_debug("%s: wait, ok=%d od=%d dk=%d dd=%d cpu=%d\n",
__func__, vctrl->ov_koff, vctrl->ov_done,
vctrl->dmap_koff, vctrl->dmap_done, smp_processor_id());
need_dmap_wait = 1;
}
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_dmap_wait) {
pr_debug("%s: wait4dmap\n", __func__);
mdp4_dsi_cmd_wait4dmap(0);
}
if (need_ov_wait) {
pr_debug("%s: wait4ov\n", __func__);
mdp4_dsi_cmd_wait4ov(0);
}
if (pipe->ov_blt_addr) {
if (vctrl->blt_end) {
vctrl->blt_end = 0;
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
}
}
if (vctrl->blt_change) {
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_dmap_xy(pipe);
vctrl->blt_change = 0;
}
pipe = vp->plist;
for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
if (pipe->pipe_used) {
cnt++;
real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
if (real_pipe && real_pipe->pipe_used) {
/* pipe not unset */
mdp4_overlay_vsync_commit(pipe);
}
/* free previous iommu to freelist
* which will be freed at next
* pipe_commit
*/
mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
pipe->pipe_used = 0; /* clear */
}
}
/* tx dcs command if had any */
mipi_dsi_cmdlist_commit(1);
mdp4_mixer_stage_commit(mixer);
pipe = vctrl->base_pipe;
#ifdef CONFIG_DISP_EXT_UTIL_VSYNC
/* TE enabled */
mdp4_mipi_vsync_enable(vctrl->mfd, pipe, 0);
#endif /*CONFIG_DISP_EXT_UTIL_VSYNC*/
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (pipe->ov_blt_addr) {
mdp4_dsi_cmd_blt_ov_update(pipe);
pipe->ov_cnt++;
vctrl->ov_koff++;
INIT_COMPLETION(vctrl->ov_comp);
vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
} else {
INIT_COMPLETION(vctrl->dmap_comp);
vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
vctrl->dmap_koff++;
}
pr_debug("%s: kickoff, pid=%d\n", __func__, current->pid);
/* kickoff overlay engine */
mdp4_stat.kickoff_ov0++;
mdp_pipe_kickoff_simplified(MDP_OVERLAY0_TERM);
mb(); /* make sure kickoff ececuted */
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
mdp4_stat.overlay_commit[pipe->mixer_num]++;
if (wait) {
if (pipe->ov_blt_addr)
mdp4_dsi_cmd_wait4ov(0);
else
mdp4_dsi_cmd_wait4dmap(0);
}
return cnt;
}
