void mdp4_mddi_overlay(void *priv, uint32_t addr, uint32_t stride,
uint32_t width, uint32_t height, uint32_t x,
uint32_t y)
{
struct mdp_info *mdp = priv;
#ifdef CONFIG_FB_MSM_WRITE_BACK
if (mdp->mdp_dev.overrides & MSM_MDP4_MDDI_DMA_SWITCH) {
mdp4_overlay_update_lcd(mdp, addr, stride, width, height, x, y);
if(mdp4_overlay_active(mdp, MDP4_MIXER0) > 1){
mdp4_overlay0_done_mddi();
mdp4_mddi_overlay_kickoff(mdp, mddi_pipe);
}
else {
if(mddi_pipe->blt_addr){
mdp4_overlay0_done_mddi();
mdp4_mddi_overlay_kickoff(mdp, mddi_pipe);
}else{
mdp4_dma_s_update_lcd(mdp);
mdp4_mddi_dma_s_kickoff(mdp, mddi_pipe);
}
}
} else {
mdp4_overlay_update_lcd(mdp, addr, stride, width, height, x, y);
mdp4_overlay0_done_mddi();
mdp4_mddi_overlay_kickoff(mdp, mddi_pipe);
}
#else
if (mdp->mdp_dev.overrides & MSM_MDP4_MDDI_DMA_SWITCH) {
mdp4_overlay_update_lcd(mdp, addr, stride, width, height, x, y);
if(mdp4_overlay_active(mdp, MDP4_MIXER0) > 1)
mdp4_mddi_overlay_kickoff(mdp, mddi_pipe);
else {
mdp4_dma_s_update_lcd(mdp);
mdp4_mddi_dma_s_kickoff(mdp, mddi_pipe);
}
} else {
mdp4_overlay_update_lcd(mdp, addr, stride, width, height, x, y);
mdp4_mddi_overlay_kickoff(mdp, mddi_pipe);
}
#endif
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
#ifdef CONFIG_SHLCDC_BOARD
uint32 data;
int master4_invalid_backupflg = master4_invalid_flg;
#endif /*CONFIG_SHLCDC_BOARD*/
#ifdef CONFIG_SHLCDC_BOARD
if(mfd->dma->busy == TRUE){
mutex_unlock(&mfd->dma->ov_mutex);
down(&mfd->sem);
up(&mfd->sem);
mutex_lock(&mfd->dma->ov_mutex);
return;
}
down(&mfd->sem);
#endif /*CONFIG_SHLCDC_BOARD*/
#ifndef CONFIG_SHLCDC_BOARD
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
#endif /*CONFIG_SHLCDC_BOARD*/
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
#ifdef CONFIG_SHLCDC_BOARD
INIT_COMPLETION(pipe->comp);
pending_pipe = pipe;
mutex_unlock(&mfd->dma->ov_mutex);
mdp_wait_vsync(mfd);
mutex_lock(&mfd->dma->ov_mutex);
#endif /*CONFIG_SHLCDC_BOARD*/
#ifdef CONFIG_SHLCDC_BOARD
if( master4_invalid_status != master4_invalid_backupflg ){
if ((mdp_hw_revision == MDP4_REVISION_V2_1) && (master4_invalid_backupflg == 0)) {
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
}else{
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
}
master4_invalid_status = master4_invalid_backupflg;
}
#endif /*CONFIG_SHLCDC_BOARD*/
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
#ifdef CONFIG_SHLCDC_BOARD
up(&mfd->sem);
/* wait until DMA finishes the current job */
if (!wait_for_completion_timeout(&pipe->comp, msecs_to_jiffies(100))) {
printk(KERN_ERR "%s: completion_timeout\n", __func__);
mdp4_overlay0_done_mddi(mfd->dma);
mdp_hw_cursor_done();
}
#endif /*CONFIG_SHLCDC_BOARD*/
}