void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
/* use dma_s pipe ,change bpp into 24 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(24 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,24);
}
#endif
mdp_enable_irq(MDP_DMA_S_TERM);
if (mddi_pipe->ov_blt_addr == 0)
mfd->dma->busy = TRUE;
mfd->ibuf_flushed = TRUE;
/* start dma_s pipe */
mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);
mdp4_stat.kickoff_dmas++;
/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
/* huawei modify */
wait_for_completion_interruptible_timeout(&mfd->dma->comp, 2 * HZ);
#else
wait_for_completion(&mfd->dma->comp);
#endif
mdp_disable_irq(MDP_DMA_S_TERM);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
/* use dma_p(overlay) pipe ,change bpp into 16 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(16 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,16);
}
#endif
/* change mdp clk while mdp is idle` */
mdp4_set_perf_level();
mdp_enable_irq(MDP_OVERLAY0_TERM);
spin_lock_irqsave(&mdp_spin_lock, flag);
mfd->dma->busy = TRUE;
if (mddi_pipe->blt_addr)
mfd->dma->dmap_busy = TRUE;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
mdp4_stat.kickoff_ov0++;
}
void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
/*< DTS2010080403325 lijianzhao 20100804 begin */
/* use dma_s pipe ,change bpp into 24 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(24 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,24);
}
#endif
/* DTS2010080403325 lijianzhao 20100804 end >*/
mdp_enable_irq(MDP_DMA_S_TERM);
mfd->dma->busy = TRUE;
mfd->ibuf_flushed = TRUE;
/* start dma_s pipe */
mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);
/* wait until DMA finishes the current job */
/* <DTS2010100802855 hufeng 20101008 begin */
#ifdef CONFIG_HUAWEI_KERNEL
/* huawei modify */
wait_for_completion_interruptible_timeout(&mfd->dma->comp, 2 * HZ);
#else
wait_for_completion(&mfd->dma->comp);
#endif
/* DTS2010100802855 hufeng 20101008 end> */
mdp_disable_irq(MDP_DMA_S_TERM);
}
void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
/* use dma_s pipe ,change bpp into 24 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(24 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,24);
}
#endif
spin_lock_irqsave(&mdp_spin_lock, flag);
if (mfd->dma->busy == TRUE) {
INIT_COMPLETION(pipe->comp);
pending_pipe = pipe;
}
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (pending_pipe != NULL) {
/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
wait_for_completion_interruptible_timeout(&pipe->comp, 1 * HZ);
#else
wait_for_completion_killable(&pipe->comp);
#endif
pending_pipe = NULL;
}
down(&mfd->sem);
mdp_enable_irq(MDP_DMA_S_TERM);
mfd->dma->busy = TRUE;
INIT_COMPLETION(pipe->dmas_comp);
mfd->ibuf_flushed = TRUE;
pending_pipe = pipe;
/* start dma_s pipe */
mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);
up(&mfd->sem);
/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
/* huawei modify */
wait_for_completion_interruptible_timeout(&pipe->dmas_comp, 2 * HZ);
#else
wait_for_completion_killable(&pipe->dmas_comp);
#endif
pending_pipe = NULL;
mdp_disable_irq(MDP_DMA_S_TERM);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
/*< DTS2010080403325 lijianzhao 20100804 begin */
/* use dma_p(overlay) pipe ,change bpp into 16 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(16 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,16);
}
#endif
/* DTS2010080403325 lijianzhao 20100804 end >*/
/*< DTS2011072603082 fengwei 20110806 begin*/
/*for resolving freeze screen because of 60 frame freq and CTS TEST*/
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
/*DTS2011072603082 fengwei 20110806 end >*/
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
#ifdef MDP4_NONBLOCKING
unsigned long flag;
/* use dma_p(overlay) pipe ,change bpp into 16 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(16 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,16);
}
#endif
if (pipe == mddi_pipe) { /* base layer */
if (mdp4_overlay_pipe_staged(pipe->mixer_num) > 1) {
if (time_before(jiffies,
(mddi_last_kick + mddi_kick_interval/2))) {
mdp4_stat.kickoff_mddi_skip++;
return; /* let other pipe to kickoff */
}
}
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (mfd->dma->busy == TRUE) {
INIT_COMPLETION(pipe->comp);
pending_pipe = pipe;
}
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (pending_pipe != NULL) {
/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
wait_for_completion_interruptible_timeout(&pipe->comp, 1 * HZ);
#else
wait_for_completion_killable(&pipe->comp);
#endif
pending_pipe = NULL;
}
down(&mfd->sem);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
if (pipe != mddi_pipe) { /* non base layer */
int intv;
if (mddi_last_kick == 0)
intv = 0;
else
intv = jiffies - mddi_last_kick;
mddi_kick_interval += intv;
mddi_kick_interval /= 2; /* average */
mddi_last_kick = jiffies;
}
up(&mfd->sem);
#else
down(&mfd->sem);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
INIT_COMPLETION(pipe->comp);
pending_pipe = pipe;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
up(&mfd->sem);
/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
wait_for_completion_interruptible_timeout(&pipe->comp, 1 * HZ);
#else
wait_for_completion_killable(&pipe->comp);
#endif
mdp_disable_irq(MDP_OVERLAY0_TERM);
#endif
}
