static void smbus_io_space_update(PIIX4PMState *s) { s->smb_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x90)); s->smb_io_base &= 0xffc0; memory_region_transaction_begin(); memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & 1); memory_region_set_address(&s->smb.io, s->smb_io_base); memory_region_transaction_commit(); }
static void rs6000mc_realize(DeviceState *dev, Error **errp) { RS6000MCState *s = RS6000MC_DEVICE(dev); int socket = 0; unsigned int ram_size = s->ram_size / MiB; while (socket < 6) { if (ram_size >= 64) { s->simm_size[socket] = 32; s->simm_size[socket + 1] = 32; ram_size -= 64; } else if (ram_size >= 16) { s->simm_size[socket] = 8; s->simm_size[socket + 1] = 8; ram_size -= 16; } else { /* Not enough memory */ break; } socket += 2; } for (socket = 0; socket < 6; socket++) { if (s->simm_size[socket]) { char name[] = "simm.?"; name[5] = socket + '0'; memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev), name, s->simm_size[socket] * MiB); memory_region_add_subregion_overlap(get_system_memory(), 0, &s->simm[socket], socket); } } if (ram_size) { /* unable to push all requested RAM in SIMMs */ error_setg(errp, "RAM size incompatible with this board. " "Try again with something else, like %" PRId64 " MB", s->ram_size / MiB - ram_size); return; } if (s->autoconfigure) { uint32_t start_address = 0; for (socket = 0; socket < 6; socket++) { if (s->simm_size[socket]) { memory_region_set_enabled(&s->simm[socket], true); memory_region_set_address(&s->simm[socket], start_address); start_address += memory_region_size(&s->simm[socket]); } } } isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, rs6000mc_port_list, s, "rs6000mc"); }
static void pm_io_space_update(PIIX4PMState *s) { PCIDevice *d = PCI_DEVICE(s); s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); s->io_base &= 0xffc0; memory_region_transaction_begin(); memory_region_set_enabled(&s->io, d->config[0x80] & 1); memory_region_set_address(&s->io, s->io_base); memory_region_transaction_commit(); }
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) { ICH9_DEBUG("to 0x%x\n", pm_io_base); assert((pm_io_base & ICH9_PMIO_MASK) == 0); pm->pm_io_base = pm_io_base; memory_region_transaction_begin(); memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); memory_region_set_address(&pm->io, pm->pm_io_base); memory_region_transaction_commit(); }
static void pm_io_space_update(PIIX4PMState *s) { uint32_t pm_io_base; pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40)); pm_io_base &= 0xffc0; memory_region_transaction_begin(); memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); memory_region_set_address(&s->io, pm_io_base); memory_region_transaction_commit(); }
static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val) { if (is_cpc_connected(gcr)) { gcr->cpc_base = val & GCR_CPC_BASE_MSK; memory_region_transaction_begin(); memory_region_set_address(gcr->cpc_mr, gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); memory_region_set_enabled(gcr->cpc_mr, gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK); memory_region_transaction_commit(); } }
static void itc_reconfigure(MIPSITUState *tag) { uint64_t *am = &tag->ITCAddressMap[0]; MemoryRegion *mr = &tag->storage_io; hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); } memory_region_set_address(mr, address); memory_region_set_enabled(mr, is_enabled); memory_region_transaction_commit(); }
static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) { RS6000MCState *s = opaque; uint8_t socket = val >> 5; uint32_t end_address = val & 0x1f; trace_rs6000mc_size_write(addr, val); s->end_address[socket] = end_address; if (socket > 0 && socket < 7) { if (s->simm_size[socket - 1]) { uint32_t size; uint32_t start_address = 0; if (socket > 1) { start_address = s->end_address[socket - 1]; } size = end_address - start_address; memory_region_set_enabled(&s->simm[socket - 1], size != 0); memory_region_set_address(&s->simm[socket - 1], start_address * 8 * MiB); } } }
/* SMRAM */ static void mch_update_smram(MCHPCIState *mch) { PCIDevice *pd = PCI_DEVICE(mch); bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); uint32_t tseg_size; /* implement SMRAM.D_LCK */ if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; } memory_region_transaction_begin(); if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { /* Hide (!) low SMRAM if H_SMRAME = 1 */ memory_region_set_enabled(&mch->smram_region, h_smrame); /* Show high SMRAM if H_SMRAME = 1 */ memory_region_set_enabled(&mch->open_high_smram, h_smrame); } else { /* Hide high SMRAM and low SMRAM */ memory_region_set_enabled(&mch->smram_region, true); memory_region_set_enabled(&mch->open_high_smram, false); } if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { memory_region_set_enabled(&mch->low_smram, !h_smrame); memory_region_set_enabled(&mch->high_smram, h_smrame); } else { memory_region_set_enabled(&mch->low_smram, false); memory_region_set_enabled(&mch->high_smram, false); } if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: tseg_size = 1024 * 1024; break; case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: tseg_size = 1024 * 1024 * 2; break; case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: tseg_size = 1024 * 1024 * 8; break; default: tseg_size = 0; break; } } else { tseg_size = 0; } memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); memory_region_set_size(&mch->tseg_blackhole, tseg_size); memory_region_add_subregion_overlap(mch->system_memory, mch->below_4g_mem_size - tseg_size, &mch->tseg_blackhole, 1); memory_region_set_enabled(&mch->tseg_window, tseg_size); memory_region_set_size(&mch->tseg_window, tseg_size); memory_region_set_address(&mch->tseg_window, mch->below_4g_mem_size - tseg_size); memory_region_set_alias_offset(&mch->tseg_window, mch->below_4g_mem_size - tseg_size); memory_region_transaction_commit(); }