void show_reset_reg(void) { unsigned long reg; /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); mfcpr(CPR0_PLLC,reg); printf("cpr_pllc = %#010lx\n",reg); mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); mfcpr(CPR0_PRIMAD0,reg); printf("cpr_primad = %#010lx\n",reg); mfcpr(CPR0_PRIMBD0,reg); printf("cpr_primbd = %#010lx\n",reg); mfcpr(CPR0_OPBD0,reg); printf("cpr_opbd = %#010lx\n",reg); mfcpr(CPR0_PERD,reg); printf("cpr_perd = %#010lx\n",reg); mfcpr(CPR0_MALD,reg); printf("cpr_mald = %#010lx\n",reg); /* read sdr register */ mfsdr(SDR0_EBC,reg); printf("SDR0_EBC = %#010lx\n",reg); mfsdr(SDR0_CP440,reg); printf("SDR0_CP440 = %#010lx\n",reg); mfsdr(SDR0_XCR,reg); printf("SDR0_XCR = %#010lx\n",reg); mfsdr(SDR0_XPLLC,reg); printf("SDR0_XPLLC = %#010lx\n",reg); mfsdr(SDR0_XPLLD,reg); printf("SDR0_XPLLD = %#010lx\n",reg); mfsdr(SDR0_PFC0,reg); printf("SDR0_PFC0 = %#010lx\n",reg); mfsdr(SDR0_PFC1,reg); printf("SDR0_PFC1 = %#010lx\n",reg); mfsdr(SDR0_CUST0,reg); printf("SDR0_CUST0 = %#010lx\n",reg); mfsdr(SDR0_CUST1,reg); printf("SDR0_CUST1 = %#010lx\n",reg); mfsdr(SDR0_UART0,reg); printf("SDR0_UART0 = %#010lx\n",reg); mfsdr(SDR0_UART1,reg); printf("SDR0_UART1 = %#010lx\n",reg); printf("===== Display reset and initialize register End =========\n"); }
void reconfigure_pll(u32 new_cpu_freq) { #if defined(CONFIG_440EPX) int reset_needed = 0; u32 reg, temp; u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ fbdv, target_fbdv, lfbdv, target_lfbdv, perdv0, target_perdv0, /* CLK_PERD */ spcid0, target_spcid0; /* CLK_SPCID */ /* Reconfigure clocks if necessary. * See PPC440EPx User's Manual, sections 8.2 and 14 */ if (new_cpu_freq == 667) { target_prbdv0 = 2; target_fwdva = 2; target_fwdvb = 4; target_fbdv = 20; target_lfbdv = 1; target_perdv0 = 4; target_spcid0 = 4; mfcpr(CPR0_PRIMBD0, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); mtcpr(CPR0_PRIMBD0, reg); reset_needed = 1; } mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; fwdva = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; fwdvb = temp ? temp : 8; temp = (reg & PLLD_FBDV_MASK) >> 24; fbdv = temp ? temp : 32; temp = (reg & PLLD_LFBDV_MASK); lfbdv = temp ? temp : 64; if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | (target_lfbdv == 64 ? 0 : target_lfbdv); mtcpr(CPR0_PLLD, reg); reset_needed = 1; } mfcpr(CPR0_PERD, reg); perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; if (perdv0 != target_perdv0) { reg &= ~CPR0_PERD_PERDV0_MASK; reg |= (target_perdv0 << 24); mtcpr(CPR0_PERD, reg); reset_needed = 1; } mfcpr(CPR0_SPCID, reg); temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; spcid0 = temp ? temp : 4; if (spcid0 != target_spcid0) { reg &= ~CPR0_SPCID_SPCIDV0_MASK; reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); mtcpr(CPR0_SPCID, reg); reset_needed = 1; } }
int board_early_init_f(void) { #ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A * First boot, with CPR0_ICFG_RLI_MASK == 0 * no we setup varios boot strapping register, * then we do reset the PPC440 using a chip reset * Unfortunately, we cannot use this option, as Nto1 is not set * with Bootstrap Option A and cannot be changed later on by SW * There are no other possible boostrap options with a 8 bit ROM * See Errata (Version 1.04) CHIP_9 */ u32 cpr0icfg; u32 dbcr; mfcpr(CPR0_ICFG, cpr0icfg); if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { mtcpr(CPR0_MALD, 0x02000000); mtcpr(CPR0_OPBD, 0x02000000); mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ mtcpr(CPR0_PLLC, 0x40000238); mtcpr(CPR0_PLLD, 0x01010414); mtcpr(CPR0_PRIMAD, 0x01000000); mtcpr(CPR0_PRIMBD, 0x01000000); mtcpr(CPR0_SPCID, 0x03000000); mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); /* * Initiate system reset in debug control register DBCR */ dbcr = mfspr(dbcr0); mtspr(dbcr0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif mtdcr(ebccfga, xbcfg); mtdcr(ebccfgd, 0xb8400000); /* * Setup the GPIO pins */ out32(GPIO0_OR, 0x00000000); out32(GPIO0_TCR, 0x7C2FF1CF); out32(GPIO0_OSRL, 0x40055000); out32(GPIO0_OSRH, 0x00000000); out32(GPIO0_TSRL, 0x40055000); out32(GPIO0_TSRH, 0x00000400); out32(GPIO0_ISR1L, 0x40000000); out32(GPIO0_ISR1H, 0x00000000); out32(GPIO0_ISR2L, 0x00000000); out32(GPIO0_ISR2H, 0x00000000); out32(GPIO0_ISR3L, 0x00000000); out32(GPIO0_ISR3H, 0x00000000); out32(GPIO1_OR, 0x00000000); out32(GPIO1_TCR, 0xC6007FFF); out32(GPIO1_OSRL, 0x00140000); out32(GPIO1_OSRH, 0x00000000); out32(GPIO1_TSRL, 0x00000000); out32(GPIO1_TSRH, 0x00000000); out32(GPIO1_ISR1L, 0x05415555); out32(GPIO1_ISR1H, 0x40000000); out32(GPIO1_ISR2L, 0x00000000); out32(GPIO1_ISR2H, 0x00000000); out32(GPIO1_ISR3L, 0x00000000); out32(GPIO1_ISR3H, 0x00000000); /* * Setup the interrupt controller polarities, triggers, etc. */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic2sr, 0xffffffff); /* clear all */ mtdcr(uic2er, 0x00000000); /* disable all */ mtdcr(uic2cr, 0x00000000); /* all non-critical */ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350); return 0; }