static long
vt6102ifstat(Ether* edev, void* a, long n, ulong offset)
{
char *p;
Ctlr *ctlr;
int i, l, r;
ctlr = edev->ctlr;
p = malloc(READSTR);
if(p == nil)
error(Enomem);
l = 0;
for(i = 0; i < Nrxstats; i++){
l += snprint(p+l, READSTR-l, "%s: %ud\n",
rxstats[i], ctlr->rxstats[i]);
}
for(i = 0; i < Ntxstats; i++){
if(txstats[i] == nil)
continue;
l += snprint(p+l, READSTR-l, "%s: %ud\n",
txstats[i], ctlr->txstats[i]);
}
l += snprint(p+l, READSTR-l, "cls: %ud\n", ctlr->cls);
l += snprint(p+l, READSTR-l, "intr: %ud\n", ctlr->intr);
l += snprint(p+l, READSTR-l, "lintr: %ud\n", ctlr->lintr);
l += snprint(p+l, READSTR-l, "lsleep: %ud\n", ctlr->lsleep);
l += snprint(p+l, READSTR-l, "rintr: %ud\n", ctlr->rintr);
l += snprint(p+l, READSTR-l, "tintr: %ud\n", ctlr->tintr);
l += snprint(p+l, READSTR-l, "taligned: %ud\n", ctlr->taligned);
l += snprint(p+l, READSTR-l, "tsplit: %ud\n", ctlr->tsplit);
l += snprint(p+l, READSTR-l, "tcopied: %ud\n", ctlr->tcopied);
l += snprint(p+l, READSTR-l, "txdw: %ud\n", ctlr->txdw);
l += snprint(p+l, READSTR-l, "tft: %ud\n", ctlr->tft);
if(ctlr->mii != nil && ctlr->mii->curphy != nil){
l += snprint(p+l, READSTR, "phy: ");
for(i = 0; i < NMiiPhyr; i++){
if(i && ((i & 0x07) == 0))
l += snprint(p+l, READSTR-l, "\n ");
r = miimir(ctlr->mii, i);
l += snprint(p+l, READSTR-l, " %4.4uX", r);
}
snprint(p+l, READSTR-l, "\n");
}
snprint(p+l, READSTR-l, "\n");
n = readstr(offset, a, n, p);
free(p);
return n;
}
static int
igbemii(Ctlr* ctlr)
{
MiiPhy *phy = (MiiPhy *)1;
int ctrl, p, r;
USED(phy);
r = csr32r(ctlr, Status);
if(r & Tbimode)
return -1;
if((ctlr->mii = malloc(sizeof(Mii))) == nil)
return -1;
ctlr->mii->ctlr = ctlr;
ctrl = csr32r(ctlr, Ctrl);
ctrl |= Slu;
switch(ctlr->id){
case i82543gc:
ctrl |= Frcdplx|Frcspd;
csr32w(ctlr, Ctrl, ctrl);
/*
* The reset pin direction (Mdro) should already
* be set from the EEPROM load.
* If it's not set this configuration is unexpected
* so bail.
*/
r = csr32r(ctlr, Ctrlext);
if(!(r & Mdro))
return -1;
csr32w(ctlr, Ctrlext, r);
delay(20);
r = csr32r(ctlr, Ctrlext);
r &= ~Mdr;
csr32w(ctlr, Ctrlext, r);
delay(20);
r = csr32r(ctlr, Ctrlext);
r |= Mdr;
csr32w(ctlr, Ctrlext, r);
delay(20);
ctlr->mii->mir = i82543miimir;
ctlr->mii->miw = i82543miimiw;
break;
case i82544ei:
case i82547ei:
case i82540em:
case i82540eplp:
case i82547gi:
case i82541gi:
case i82541pi:
case i82546gb:
case i82546eb:
ctrl &= ~(Frcdplx|Frcspd);
csr32w(ctlr, Ctrl, ctrl);
ctlr->mii->mir = igbemiimir;
ctlr->mii->miw = igbemiimiw;
break;
default:
free(ctlr->mii);
ctlr->mii = nil;
return -1;
}
if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
if (0)
print("phy trouble: phy = 0x%lux\n", (uint32_t)phy);
free(ctlr->mii);
ctlr->mii = nil;
return -1;
}
//print("oui %X phyno %d\n", phy->oui, phy->phyno);
USED(phy);
/*
* 8254X-specific PHY registers not in 802.3:
* 0x10 PHY specific control
* 0x14 extended PHY specific control
* Set appropriate values then reset the PHY to have
* changes noted.
*/
switch(ctlr->id){
case i82547gi:
case i82541gi:
case i82541pi:
case i82546gb:
case i82546eb:
break;
default:
r = miimir(ctlr->mii, 16);
r |= 0x0800; /* assert CRS on Tx */
r |= 0x0060; /* auto-crossover all speeds */
r |= 0x0002; /* polarity reversal enabled */
miimiw(ctlr->mii, 16, r);
r = miimir(ctlr->mii, 20);
r |= 0x0070; /* +25MHz clock */
r &= ~0x0F00;
r |= 0x0100; /* 1x downshift */
miimiw(ctlr->mii, 20, r);
miireset(ctlr->mii);
break;
}
p = 0;
if(ctlr->txcw & TxcwPs)
p |= AnaP;
if(ctlr->txcw & TxcwAs)
p |= AnaAP;
miiane(ctlr->mii, ~0, p, ~0);
return 0;
}
