int hieth_mdiobus_driver_init(void)
{
mdio_bus_ld.iobase_phys = ETH_IO_ADDRESS_BASE;
mdio_bus_ld.mdio_frqdiv = ETH_MDIO_FRQDIV;
hieth_mdio_init(&mdio_bus_ld);
/* UpEther PHY init */
miiphy_register(U_PHY_NAME, hieth_mdiobus_read, hieth_mdiobus_write);
if(!get_phy_device(U_PHY_NAME,U_PHY_ADDR))
{
miiphy_reset(U_PHY_NAME, U_PHY_ADDR);
miiphy_set_current_dev(U_PHY_NAME);
}
/* DownEther PHY init */
miiphy_register(D_PHY_NAME, hieth_mdiobus_read, hieth_mdiobus_write);
if(!get_phy_device(D_PHY_NAME,D_PHY_ADDR))
{
miiphy_reset(D_PHY_NAME, D_PHY_ADDR);
miiphy_set_current_dev(D_PHY_NAME);
}
return 0;
}
/* Configure and enable MV88E1318 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__FUNCTION__);
return;
}
/* Set RGMII delay */
miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®);
reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("MV88E1318 PHY initialized on %s\n", name);
}
static void mv_phy_88e1118_init(char *name)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1118 Initialized on %s\n", name);
}
void mv_phy_88e1318_init(const char *name, u16 phyaddr)
{
u16 reg;
if (miiphy_set_current_dev(name))
return;
/*
* Set control mode 4 for LED[0].
*/
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
miiphy_read(name, phyaddr, 16, ®);
reg |= 0xf;
miiphy_write(name, phyaddr, 16, reg);
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
if (miiphy_reset(name, phyaddr) == 0)
printf("88E1318 Initialized on %s\n", name);
}
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
{
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
void reset_phy(void)
{
#if defined(CONFIG_KM_MVEXTSW_ADDR)
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
ARRAY_SIZE(extsw_conf));
mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
#endif
}
int last_stage_init(void)
{
#if defined(CONFIG_KMVECT1)
struct km_bec_fpga __iomem *base =
(struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
u8 tmp_reg;
/* Release mv88e6122 from reset */
tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
out_8(&base->res1[0], tmp_reg); /* GP28 as output */
tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
out_8(&base->gprt3, tmp_reg);
/* configure MV88E6122 switch */
char *name = "UEC2";
if (miiphy_set_current_dev(name))
return 0;
mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
ARRAY_SIZE(extsw_conf));
mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
if (piggy_present()) {
setenv("ethact", "UEC2");
setenv("netdev", "eth1");
puts("using PIGGY for network boot\n");
} else {
setenv("netdev", "eth0");
puts("using frontport for network boot\n");
}
#endif
#if defined(CONFIG_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {
/* start bootloader */
puts("DIP: Enabled\n");
setenv("actual_bank", "0");
}
#endif
set_km_env();
return 0;
}
int stmmac_mdiobus_driver_init(void)
{
stmmac_mdio_local_device.iobase_phys = STMMAC_MDIO_IO_BASE;
stmmac_mdio_local_device.iobase = STMMAC_MDIO_IO_BASE;
stmmac_mdio_clk_init(&stmmac_mdio_local_device);
/* GMAC0 PHY init */
miiphy_register(GMAC0_PHY_NAME, stmmac_mdiobus_read,
stmmac_mdiobus_write);
if (!get_phy_device(GMAC0_PHY_NAME, GMAC0_PHY_ADDR))
miiphy_set_current_dev(GMAC0_PHY_NAME);
return 0;
}
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
{
unsigned int oui;
unsigned char model, rev;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
/* get PHY model */
if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
return;
/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
if ((oui == PHY_MARVELL_OUI) &&
(model == PHY_MARVELL_88E1118R_MODEL)) {
/* set page register to 3 */
if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
PHY_MARVELL_PAGE_REG,
PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
printf("Error writing PHY page reg\n");
/*
* leds setup as printed on PCB:
* LED2 (Link): 0x0 (On Link, Off No Link)
* LED1 (Activity): 0x3 (On Activity, Off No Activity)
* LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
*/
if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
PHY_MARVELL_88E1118R_LED_CTRL_REG,
PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
printf("Error writing PHY LED reg\n");
/* set page register back to 0 */
if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
PHY_MARVELL_PAGE_REG,
PHY_MARVELL_DEFAULT_PAGE))
printf("Error writing PHY page reg\n");
}
}
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
{
char *name = "egiga0";
unsigned short reg;
if (miiphy_set_current_dev(name))
return;
/* RGMII clk transition on data stable */
if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
printf("Error reading PHY spec ctrl reg\n");
if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
printf("Error writing PHY LED reg\n");
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
void mv_phy_88e1116_init(char *name)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__FUNCTION__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) {
printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
return;
}
if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
return;
}
printf("88E1116 Initialized on %s\n", name);
}
/*
* Marvell 88E61XX Switch initialization
*/
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
{
u32 prt;
u16 reg;
char *idstr;
char *name = swconfig->name;
int time;
if (miiphy_set_current_dev(name)) {
printf("%s failed\n", __FUNCTION__);
return -1;
}
if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
swconfig->cpuport = (1 << 5);
printf("Invalid cpu port config, using default port5\n");
}
RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®);
switch (reg &= 0xfff0) {
case 0x1610:
idstr = "88E6161";
break;
case 0x1650:
idstr = "88E6165";
break;
case 0x1210:
idstr = "88E6123";
/* ports 2,3,4 not available */
swconfig->ports_enabled &= 0x023;
break;
default:
/* Could not detect switch id */
idstr = "88E61??";
break;
}
/* be sure all ports are disabled */
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®);
reg &= ~0x3;
WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
}
/* wait 2 ms for queues to drain */
udelay(2000);
/* reset switch */
RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®);
reg |= 0x8000;
WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
/* wait up to 1 second for switch reset complete */
for (time = 1000; time; time--) {
RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
®);
if ((reg & 0xc800) == 0xc800)
break;
udelay(1000);
}
if (!time)
return -1;
/* Port based VLANs configuration */
mv88e61xx_port_vlan_config(swconfig);
if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 9.5 of chip datasheet-02
*/
/*Force port link down */
WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
/* configure port RGMII delay */
WR_SWITCH_PORT_REG(name, 4,
MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
RD_SWITCH_PORT_REG(name, 5,
MV88E61XX_RGMII_TIMECTRL_REG, ®);
WR_SWITCH_PORT_REG(name, 5,
MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
WR_SWITCH_PORT_REG(name, 4,
MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
/* Force port to RGMII FDX 1000Base then up */
WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
}
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
/* configure port's PHY */
if (!((1 << prt) & swconfig->cpuport)) {
/* port 4 has phy 6, not 4 */
int phy = (prt == 4) ? 6 : prt;
if (mv88361xx_powerup(swconfig, phy))
return -1;
if (mv88361xx_reverse_mdipn(swconfig, phy))
return -1;
if (mv88361xx_led_init(swconfig, phy))
return -1;
}
/* set port VID to port+1 except for cpu port */
if (!((1 << prt) & swconfig->cpuport)) {
RD_SWITCH_PORT_REG(name, prt,
MV88E61XX_PRT_VID_REG, ®);
WR_SWITCH_PORT_REG(name, prt,
MV88E61XX_PRT_VID_REG,
(reg & ~1023) | (prt+1));
}
/*Program port state */
RD_SWITCH_PORT_REG(name, prt,
MV88E61XX_PRT_CTRL_REG, ®);
WR_SWITCH_PORT_REG(name, prt,
MV88E61XX_PRT_CTRL_REG,
reg | (swconfig->portstate & 0x03));
}
printf("%s Initialized on %s\n", idstr, name);
return 0;
}
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
int i, j;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
switch (dpmac) {
case 1:
case 2:
case 3:
case 4:
i2c_phy_addr = i2c_addr[0];
phy_addr = 0;
break;
case 5:
case 6:
case 7:
case 8:
i2c_phy_addr = i2c_addr[1];
phy_addr = 4;
break;
case 9:
case 10:
case 11:
case 12:
i2c_phy_addr = i2c_addr[2];
phy_addr = 8;
break;
case 13:
case 14:
case 15:
case 16:
i2c_phy_addr = i2c_addr[3];
phy_addr = 0xc;
break;
}
/* Check the PHY status */
ret = miiphy_set_current_dev(dev);
ret = miiphy_write(dev, phy_addr, 0x1f, 3);
mdelay(10);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
mdelay(10);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
mdelay(10);
if ((value & 0xf) == 0xf) {
printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
return;
}
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(1);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
mdelay(10);
if ((value & 0xf) == 0xf) {
printf("DPMAC %d :PHY is ..... Configured\n",
dpmac);
return;
}
}
}
error:
printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
return;
}
/*
* Marvell 88E61XX Switch initialization
*/
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
{
u32 prt;
u16 reg;
char *idstr;
char *name = swconfig->name;
if (miiphy_set_current_dev(name)) {
printf("%s failed\n", __FUNCTION__);
return -1;
}
if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
swconfig->cpuport = (1 << 5);
printf("Invalid cpu port config, using default port5\n");
}
RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®);
reg &= 0xfff0;
if (reg == 0x1610)
idstr = "88E6161";
if (reg == 0x1650)
idstr = "88E6165";
if (reg == 0x1210) {
idstr = "88E6123";
/* ports 2,3,4 not available */
swconfig->ports_enabled &= 0x023;
}
/* Port based VLANs configuration */
if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
|| (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
MV88E61XX_PRT_OFST);
else {
printf("Unsupported mode %s failed\n", __FUNCTION__);
return -1;
}
if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 9.5 of chip datasheet-02
*/
WR_PHY(name, MV88E61XX_PRT_OFST + 5,
MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
WR_PHY(name, MV88E61XX_PRT_OFST + 4,
MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
}
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
if (!((1 << prt) & swconfig->cpuport)) {
if (mv88361xx_led_init(swconfig, prt))
return -1;
if (mv88361xx_reverse_mdipn(swconfig, prt))
return -1;
if (mv88361xx_powerup(swconfig, prt))
return -1;
}
/*Program port state */
RD_PHY(name, MV88E61XX_PRT_OFST + prt,
MV88E61XX_PRT_CTRL_REG, ®);
WR_PHY(name, MV88E61XX_PRT_OFST + prt,
MV88E61XX_PRT_CTRL_REG,
reg | (swconfig->portstate & 0x03));
}
printf("%s Initialized on %s\n", idstr, name);
return 0;
}
/*
* MII device/info/read/write
*
* Syntax:
* mii device {devname}
* mii info {addr}
* mii read {addr} {reg}
* mii write {addr} {reg} {data}
*/
int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
unsigned char addr, reg;
unsigned short data;
int rcode = 0;
char *devname;
if (argc < 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
#endif
/*
* We use the last specified parameters, unless new ones are
* entered.
*/
op = last_op;
addr = last_addr;
data = last_data;
reg = last_reg;
if ((flag & CMD_FLAG_REPEAT) == 0) {
op = argv[1][0];
if (argc >= 3)
addr = simple_strtoul (argv[2], NULL, 16);
if (argc >= 4)
reg = simple_strtoul (argv[3], NULL, 16);
if (argc >= 5)
data = simple_strtoul (argv[4], NULL, 16);
}
/* use current device */
devname = miiphy_get_current_dev();
/*
* check device/read/write/list.
*/
if (op == 'i') {
unsigned char j, start, end;
unsigned int oui;
unsigned char model;
unsigned char rev;
/*
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
start = addr; end = addr + 1;
} else {
start = 0; end = 31;
}
for (j = start; j < end; j++) {
if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
printf ("PHY 0x%02X: "
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbase%s, %s\n",
j, oui, model, rev,
miiphy_speed (devname, j),
miiphy_is_1000base_x (devname, j)
? "X" : "T",
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
}
}
} else if (op == 'r') {
if (miiphy_read (devname, addr, reg, &data) != 0) {
puts ("Error reading from the PHY\n");
rcode = 1;
} else {
printf ("%04X\n", data & 0x0000FFFF);
}
} else if (op == 'w') {
if (miiphy_write (devname, addr, reg, data) != 0) {
puts ("Error writing to the PHY\n");
rcode = 1;
}
} else if (op == 'd') {
if (argc == 2)
miiphy_listdev ();
else
miiphy_set_current_dev (argv[2]);
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/*
* Save the parameters for repeats.
*/
last_op = op;
last_addr = addr;
last_data = data;
last_reg = reg;
return rcode;
}
static void sgmii_configure_repeater(int serdes_port)
{
struct mii_dev *bus;
uint8_t a = 0xf;
int i, j, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
for (dpmac = 0; dpmac < 8; dpmac++) {
/* Check the PHY status */
switch (serdes_port) {
case 1:
mii_bus = 0;
dpmac_id = dpmac + 1;
break;
case 2:
mii_bus = 1;
dpmac_id = dpmac + 9;
a = 0xb;
i2c_write(0x76, 0, 0, &a, 1);
break;
}
ret = miiphy_set_current_dev(dev[mii_bus]);
if (ret > 0)
goto error;
bus = mdio_get_current_dev();
debug("Reading from bus %s\n", bus->name);
ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
3);
if (ret > 0)
goto error;
mdelay(10);
ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
&value);
if (ret > 0)
goto error;
mdelay(10);
if ((value & 0xfff) == 0x40f) {
printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
continue;
}
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
i2c_write(i2c_addr[dpmac], 0xf, 1,
&ch_a_eq[i], 1);
i2c_write(i2c_addr[dpmac], 0x11, 1,
&ch_a_ctl2[j], 1);
i2c_write(i2c_addr[dpmac], 0x16, 1,
&ch_b_eq[i], 1);
i2c_write(i2c_addr[dpmac], 0x18, 1,
&ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev[mii_bus],
riser_phy_addr[dpmac],
0x11, &value);
if (ret > 0)
goto error;
mdelay(1);
ret = miiphy_read(dev[mii_bus],
riser_phy_addr[dpmac],
0x11, &value);
if (ret > 0)
goto error;
mdelay(10);
if ((value & 0xfff) == 0x40f) {
printf("DPMAC %d :PHY is configured ",
dpmac_id);
printf("after setting repeater 0x%x\n",
value);
i = 5;
j = 5;
} else
printf("DPMAC %d :PHY is failed to ",
dpmac_id);
printf("configure the repeater 0x%x\n",
value);
}
}
}
error:
if (ret)
printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
return;
}
/* ---------------------------------------------------------------- */
static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char op[2];
int addrlo, addrhi, reglo, reghi, devadlo, devadhi;
unsigned short data;
int pos = argc - 1;
struct mii_dev *bus;
struct phy_device *phydev = NULL;
int extended = 0;
if (argc < 2)
return CMD_RET_USAGE;
/*
* We use the last specified parameters, unless new ones are
* entered.
*/
op[0] = argv[1][0];
addrlo = last_addr_lo;
addrhi = last_addr_hi;
devadlo = last_devad_lo;
devadhi = last_devad_hi;
reglo = last_reg_lo;
reghi = last_reg_hi;
data = last_data;
bus = mdio_get_current_dev();
if (flag & CMD_FLAG_REPEAT)
op[0] = last_op[0];
if (strlen(argv[1]) > 1) {
op[1] = argv[1][1];
if (op[1] == 'x') {
phydev = mdio_phydev_for_ethname(argv[2]);
if (phydev) {
addrlo = phydev->addr;
addrhi = addrlo;
bus = phydev->bus;
extended = 1;
} else {
return CMD_RET_FAILURE;
}
if (!phydev->drv ||
(!phydev->drv->writeext && (op[0] == 'w')) ||
(!phydev->drv->readext && (op[0] == 'r'))) {
puts("PHY does not have extended functions\n");
return CMD_RET_FAILURE;
}
}
}
switch (op[0]) {
case 'w':
if (pos > 1)
data = simple_strtoul(argv[pos--], NULL, 16);
case 'r':
if (pos > 1)
if (extract_reg_range(argv[pos--], &devadlo, &devadhi,
®lo, ®hi))
return CMD_RET_FAILURE;
default:
if (pos > 1)
if (extract_phy_range(&argv[2], pos - 1, &bus,
&phydev, &addrlo, &addrhi))
return CMD_RET_FAILURE;
break;
}
if (op[0] == 'l') {
mdio_list_devices();
return 0;
}
/* Save the chosen bus */
miiphy_set_current_dev(bus->name);
switch (op[0]) {
case 'w':
mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi,
reglo, reghi, data, extended);
break;
case 'r':
mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi,
reglo, reghi, extended);
break;
}
/*
* Save the parameters for repeats.
*/
last_op[0] = op[0];
last_addr_lo = addrlo;
last_addr_hi = addrhi;
last_devad_lo = devadlo;
last_devad_hi = devadhi;
last_reg_lo = reglo;
last_reg_hi = reghi;
last_data = data;
return 0;
}
