int mipi_config(struct msm_fb_panel_data *panel)
{
int ret = NO_ERROR;
#if (DISPLAY_TYPE_MDSS == 0)
struct msm_panel_info *pinfo;
struct mipi_dsi_panel_config mipi_pinfo;
if (!panel)
return ERR_INVALID_ARGS;
pinfo = &(panel->panel_info);
mipi_pinfo.mode = pinfo->mipi.mode;
mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db;
mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds;
mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
mipi_pinfo.pack = 1;
/* Enable MMSS_AHB_ARB_MATER_PORT_E for
arbiter master0 and master 1 request */
#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610)
writel(0x00001800, MMSS_SFPB_GPREG);
#endif
mipi_dsi_phy_init(&mipi_pinfo);
ret += mipi_dsi_panel_initialize(&mipi_pinfo);
if (pinfo->rotate && panel->rotate)
pinfo->rotate();
#endif
return ret;
}
struct fbcon_config *mipi_init(void)
{
int status = 0;
struct mipi_dsi_panel_config *panel_info = get_panel_info();
/* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
#if (!DISPLAY_MIPI_PANEL_RENESAS)
writel(0x00001800, MMSS_SFPB_GPREG);
#endif
#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
mipi_dsi_phy_init(panel_info);
#else
mipi_dsi_phy_ctrl_config(panel_info);
#endif
status += mipi_dsi_panel_initialize(panel_info);
#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
mipi_dsi_cmd_bta_sw_trigger();
mipi_novatek_manufacture_id();
#endif
mipi_fb_cfg.base = MIPI_FB_ADDR;
if (panel_info->mode == MIPI_VIDEO_MODE)
status += mipi_dsi_video_config(panel_info->num_of_lanes);
if (panel_info->mode == MIPI_CMD_MODE)
cmd_mode_status = 1;
return &mipi_fb_cfg;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
#ifdef CONFIG_HUAWEI_KERNEL
unsigned int datamask = 0;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
local_bh_disable();
mipi_dsi_ahb_ctrl(1);
local_bh_enable();
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
/*
* It because of the reset and clock order,
* that Qualcomm baseband will be issued a special waveform,
* this cause the lcd enter the wrong state and data 0 will be pulled low,
* and mipi dsi will work abnormal.
*/
#ifdef CONFIG_HUAWEI_KERNEL
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
/*
* It because of the reset and clock order,
* that Qualcomm baseband will be issued a special waveform,
* this cause the lcd enter the wrong state and data 0 will be pulled low,
* and mipi dsi will work abnormal.
*/
#ifndef CONFIG_HUAWEI_KERNEL
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#endif
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#ifdef CONFIG_HUAWEI_KERNEL
/*when here there is a wrong sequence bofore ,so add 5 ms hope lcd panel can enter the right mode */
mdelay(5);
/* request data line and clock line to exit the ulps mode */
if (mipi->data_lane3)
datamask |= 1<<11;
if (mipi->data_lane2)
datamask |= 1<<10;
if (mipi->data_lane1)
datamask |= 1<<9;
if (mipi->data_lane0)
datamask |= 1<<8;
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask | (1<<12));
/* It is the mipi request ,at least 1 ms*/
mdelay(2);
/*absolutely exit the ulps mode */
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0);
#endif
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev >= MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->op_enable)
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
u32 tmp;
int target_type = 0;
int old_nice;
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
/*
* Now first priority is to turn on LCD quickly for better
* user experience. We set current task to higher priority
* and restore it after panel is on.
*/
old_nice = task_nice(current);
if (old_nice > -20)
set_user_nice(current, -20);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
#if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11)
/*
* Fix for floating state of VDD line in toshiba chip
* */
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save)
mipi_dsi_pdata->dsi_client_power_save(1);
#endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_ahb_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11)
/*
* For TC358764 D2L IC, one of the requirement for power on
* is to maintain an LP11 state in data and clock lanes during
* power enabling and reset assertion. This change is to
* achieve that.
* */
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save) {
u32 tmp_reg0c, tmp_rega8;
mipi_dsi_pdata->dsi_client_reset();
udelay(200);
/* backup register values */
tmp_reg0c = MIPI_INP(MIPI_DSI_BASE + 0x000c);
tmp_rega8 = MIPI_INP(MIPI_DSI_BASE + 0xA8);
/* Clear HS mode assertion and related flags */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x8000);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x0);
wmb();
mdelay(5);
/* restore previous values */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, tmp_reg0c);
MIPI_OUTP(MIPI_DSI_BASE + 0xa8, tmp_rega8);
wmb();
}
#endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */
#if defined(CONFIG_FB_MSM_MIPI_MAGNA_OLED_VIDEO_WVGA_PT)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(); /* high */
usleep(10000);
#endif
if (mipi->force_clk_lane_hs) {
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
// clk struck error msg p13447 Shinjg 201205
cont_splash_clk_ctrl();
local_bh_disable();
mipi_dsi_ahb_ctrl(1);
local_bh_enable();
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if 0
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
#endif
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#ifdef CONFIG_F_SKYDISP_SILENT_BOOT
if(!backlight_value)
#endif
#if 0//defined (CONFIG_MACH_MSM8960_MAGNUS)
mipi_dsi_op_mode_config(mipi->mode);
msleep(35);
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
#endif
//#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE) || defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE) || defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS)
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
printk("[MIPI: shinbrad High speed Clk Set .................................................]\n");
}
#endif
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */
printk(KERN_ERR "%s: clk_set_rate failed\n",
__func__);
clk_enable(amp_pclk);
clk_enable(dsi_m_pclk);
clk_enable(dsi_byte_div_clk);
clk_enable(dsi_esc_clk);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_ahb_en();
mipi_dsi_sfpb_cfg();
mipi_dsi_clk(1);
mipi_dsi_pclk(1);
mipi_dsi_phy_init(0); /* toshiba video */
enable_irq(DSI_IRQ);
/*
* turn esc, byte, dsi, pclk, sclk, hclk on
*/
MIPI_OUTP(MIPI_DSI_BASE + 0x118, 0x23f); /* DSI_CLK_CTRL */
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width - 1) << 16 | (hbp - 1)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height - 1) << 16 | (vbp - 1)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + vfp - 1) << 16 |
(hbp + width + hfp - 1));
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw - 1) << 16);
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw - 1) << 16);
/* there has hardware problem
* the color channel between dsi and mdp are swapped
*/
MIPI_OUTP(MIPI_DSI_BASE + 0x1c, 0x2000); /* rGB --> BGR */
/* embedded mode, lpm */
MIPI_OUTP(MIPI_DSI_BASE + 0x38, 0x14000000);
/* non burst sync pulse, 888RGB */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x11119030);
}
MIPI_OUTP(MIPI_DSI_BASE + 0x0080, 0x04);/* sw trigger */
/* command mode */
MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0x135);
wmb();
ret = panel_next_on(pdev);
/* video mode */
MIPI_OUTP(MIPI_DSI_BASE + 0x0, 0x133);
wmb();
pm_qos_update_request(mfd->pm_qos_req, 122000);
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
u32 tmp;
#endif
pr_info("%s+:\n", __func__);
#if defined(CONFIG_MIPI_SAMSUNG_ESD_REFRESH) || defined(CONFIG_ESD_ERR_FG_RECOVERY)
pdev_for_esd = pdev;
#endif
#ifdef CONFIG_DUAL_LCD
if (mipi_dsi_pdev_switch == NULL)
pr_debug( "%s : pdev_switch updated", __func__ );
mipi_dsi_pdev_switch = pdev;
#endif // #ifdef CONFIG_DUAL_LCD
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return ENODEV;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
#if defined(CONFIG_MACH_LT02_CHN_CTC)
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(4000);
ret = panel_next_on(pdev);
usleep(1000);
#endif
mipi_dsi_prepare_ahb_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT_PANEL)
mipi_dsi_configure_dividers(60);
#endif
#if defined(CONFIG_RUNTIME_MIPI_CLK_CHANGE) && defined(CONFIG_FB_MSM_MIPI_AMS367_OLED_VIDEO_WVGA_PT_PANEL)
if (is_S6E88A())
mipi_AMS367AV_dynamic_fps_folder(in_mipi_dsi_NULL, pinfo);
else
mipi_AMS367_dynamic_fps_folder(in_mipi_dsi_NULL, pinfo);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(10000);
#endif
#endif
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT)
if(system_rev)
ret = panel_next_on(pdev);
#endif
if (mipi->force_clk_lane_hs) {
#ifndef CONFIG_MIPI_DSI_RESET_LP11
u32 tmp;
#endif
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT)
if(!system_rev)
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
#endif
#endif
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
int old_nice;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
/*
* Now first priority is to turn on LCD quickly for better
* user experience. We set current task to higher priority
* and restore it after panel is on.
*/
old_nice = task_nice(current);
if (old_nice > -20)
set_user_nice(current, -20);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi = &mfd->panel_info.mipi;
/* Clean up the force clk lane to enter HS from previous boot */
if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
mipi->force_clk_lane_hs)
MIPI_OUTP(MIPI_DSI_BASE + 0x00a8, 0);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
/*
* The MIPI host is done with INIT now, the lines are at LP-11,
* and it is safe to turn on the power to the panel and get it out
* of reset
*/
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(1);
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#ifndef CONFIG_FB_MSM_MDP303
mdp4_overlay_dsi_state_set(ST_DSI_RESUME);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
mipi_dsi_cmd_bta_sw_trigger(); /* clean up ack_err_status */
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
if (gpio_request(vsync_gpio, "MDP_VSYNC") == 0)
gpio_direction_input(vsync_gpio);
else
pr_err("%s: unable to request gpio=%d\n",
__func__, vsync_gpio);
}
mipi_dsi_set_tear_on(mfd);
}
}
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(2);
#endif
return ret;
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
u32 tmp;
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
static int is_booting = 1;
#endif
#ifdef CONFIG_FB_MSM_LCD_NOTIFY
lcd_notifier_call_chain(LCD_EVENT_ON_START, NULL);
#endif
pr_debug("%s+:\n", __func__);
#if defined(CONFIG_MIPI_SAMSUNG_ESD_REFRESH) || defined(CONFIG_ESD_ERR_FG_RECOVERY)
pdev_for_esd = pdev;
#endif
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return ENODEV;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mipi_dsi_pdata && mipi_dsi_pdata->power_common)
mipi_dsi_pdata->power_common();
#if defined(CONFIG_SUPPORT_SECOND_POWER)
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
if( is_booting == 1 )
{
is_booting = 0;
#if defined(CONFIG_MACH_JACTIVE_ATT) || defined(CONFIG_MACH_JACTIVE_EUR)
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(0); /* low */
usleep(2000);
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(0);
msleep(10);
#endif
}
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(1);
#endif
#if !defined(CONFIG_SEC_PRODUCT_8930) && !defined(CONFIG_SEC_PRODUCT_8960)
if (system_rev == 6)
mdelay(500);
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT_PANEL)
mipi_dsi_configure_dividers(60);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT_PANEL)
{
u32 tmp_reg0c, tmp_rega8;
udelay(200);
/* backup register values */
tmp_reg0c = MIPI_INP(MIPI_DSI_BASE + 0x000c);
tmp_rega8 = MIPI_INP(MIPI_DSI_BASE + 0xA8);
/* Clear HS mode assertion and related flags */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x8000);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x0);
wmb();
mdelay(10);
if (mipi_dsi_pdata && mipi_dsi_pdata->lcd_rst_up)
mipi_dsi_pdata->lcd_rst_up();
/* restore previous values */
MIPI_OUTP(MIPI_DSI_BASE + 0x0c, tmp_reg0c);
MIPI_OUTP(MIPI_DSI_BASE + 0xa8, tmp_rega8);
wmb();
}
#else
msleep(10);
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
/* LP11 */
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp &= ~(1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
/* LP11 */
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(1); /* high */
usleep(10000);
#endif
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT) || defined(CONFIG_MACH_LT02_TMO)
if(system_rev)
ret = panel_next_on(pdev);
#elif defined(CONFIG_MACH_LT02_CHN_CTC)
ret = panel_next_on(pdev);
#endif
#endif
/* always high */
if (mipi->force_clk_lane_hs) {
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
#if !defined(CONFIG_MACH_LT02_CHN_CTC)
#if defined(CONFIG_MACH_LT02_SPR) || defined(CONFIG_MACH_LT02_ATT) || defined(CONFIG_MACH_LT02_TMO)
if(!system_rev)
ret = panel_next_on(pdev);
#else
ret = panel_next_on(pdev);
#endif
#endif
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
local_bh_disable();
mipi_dsi_clk_enable();
local_bh_enable();
#ifndef CONFIG_FB_MSM_MDP303
mdp4_overlay_dsi_state_set(ST_DSI_RESUME);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
mfd->dma->busy = FALSE;//add by Wenke Ma, as zygote died and restart then the isr cannot enter and this flag doesnot set false
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.mipi.xres_pad;
dummy_yres = mfd->panel_info.mipi.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
/* DSI_LAN_SWAP_CTRL */
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else { /* command mode */
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3; /* Default format set to RGB888 */
ystride = width * bpp + 1;
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi);
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
printk("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mfd->first_init_lcd == 0) {
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
height = mfd->panel_info.yres;
mipi = &mfd->panel_info.mipi;
if (mfd->panel_info.type == MIPI_VIDEO_PANEL) {
dummy_xres = mfd->panel_info.lcdc.xres_pad;
dummy_yres = mfd->panel_info.lcdc.yres_pad;
if (mdp_rev >= MDP_REV_41) {
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hspw + hbp + width + dummy_xres) << 16 |
(hspw + hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vspw + vbp + height + dummy_yres) << 16 |
(vspw + vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vspw + vbp + height + dummy_yres +
vfp - 1) << 16 | (hspw + hbp +
width + dummy_xres + hfp - 1));
} else {
MIPI_OUTP(MIPI_DSI_BASE + 0x00ac,
mipi_dsi_pdata->dlane_swap);
MIPI_OUTP(MIPI_DSI_BASE + 0x20,
((hbp + width + dummy_xres) << 16 | (hbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x24,
((vbp + height + dummy_yres) << 16 | (vbp)));
MIPI_OUTP(MIPI_DSI_BASE + 0x28,
(vbp + height + dummy_yres + vfp) << 16 |
(hbp + width + dummy_xres + hfp));
}
MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16));
MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0);
MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16));
} else {
if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
bpp = 3;
else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
bpp = 2;
else
bpp = 3;
ystride = width * bpp + 1;
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x54, data);
data = height << 16 | width;
MIPI_OUTP(MIPI_DSI_BASE + 0x60, data);
MIPI_OUTP(MIPI_DSI_BASE + 0x58, data);
}
mipi_dsi_host_init(mipi, mipi_dsi_pdata->dlane_swap);
if (mipi->force_clk_lane_hs) {
u32 tmp;
tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8);
tmp |= (1<<28);
MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp);
wmb();
}
#if defined(CONFIG_MACH_DUMMY)
if ((panel_type == PANEL_ID_PROTODCG_SHARP || panel_type == PANEL_ID_PROTODCG_SHARP_C1) &&
mfd->first_init_lcd != 0) {
protodcg_orise_lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
#elif defined(CONFIG_MACH_PROTOU)
if ((panel_type == PANEL_ID_PROTOU_SHARP || panel_type == PANEL_ID_PROTOU_SHARP_C1) &&
mfd->first_init_lcd != 0) {
protou_orise_lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
#endif
if (panel_type == PANEL_ID_URANUS_SONY_ORISE) {
if(mfd->first_init_lcd != 0) {
if (mipi_dsi_pdata && mipi_dsi_pdata->lcd_pre_off)
mipi_dsi_pdata->lcd_pre_off(pdev);
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
}
}
ret = panel_next_on(pdev);
mipi_dsi_op_mode_config(mipi->mode);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (mdp_rev >= MDP_REV_41) {
if (gpio_request(vsync_gpio,
"MDP_VSYNC") == 0)
gpio_direction_input(
vsync_gpio);
else
pr_err("%s: unable to \
request gpio=%d\n",
__func__, vsync_gpio);
} else if (mdp_rev == MDP_REV_303) {
if (!tlmm_settings && gpio_request(
vsync_gpio, "MDP_VSYNC") == 0) {
ret = gpio_tlmm_config(
GPIO_CFG(
vsync_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (ret) {
pr_err(
"%s: unable to config \
tlmm = %d\n",
__func__, vsync_gpio);
}
tlmm_settings = TRUE;
gpio_direction_input(
vsync_gpio);
} else {
if (!tlmm_settings) {
pr_err(
"%s: unable to request \
gpio=%d\n",
__func__, vsync_gpio);
}
}
}