void mipi_dsi_clk_enable(void) { u32 pll_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0200); if (mipi_dsi_clk_on) { pr_info("%s: mipi_dsi_clks already ON\n", __func__); return; } MIPI_OUTP(MIPI_DSI_BASE + 0x0200, pll_ctrl | 0x01); mipi_dsi_phy_rdy_poll(); if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */ pr_err("%s: dsi_byte_div_clk - " "clk_set_rate failed\n", __func__); if (clk_set_rate(dsi_esc_clk, esc_byte_ratio) < 0) /* divided by esc */ pr_err("%s: dsi_esc_clk - " /* clk ratio */ "clk_set_rate failed\n", __func__); mipi_dsi_pclk_ctrl(&dsi_pclk, 1); mipi_dsi_clk_ctrl(&dsicore_clk, 1); clk_enable(dsi_byte_div_clk); clk_enable(dsi_esc_clk); mipi_dsi_clk_on = 1; mdp4_stat.dsi_clk_on++; #ifdef CONFIG_SHLCDC_BOARD /* CUST_ID_00097 */ SHLCDC_EVENTLOG_REC(FB,LCD,MSM_FB_KERL,EEVENTID_FB_DSI_CLK_ENABLE,0); #endif /* CONFIG_SHLCDC_BOARD */ }
void mipi_dsi_clk_enable(void) { u32 pll_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0200); MIPI_OUTP(MIPI_DSI_BASE + 0x0200, pll_ctrl | 0x01); mipi_dsi_phy_rdy_poll(); if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */ pr_err("%s: dsi_byte_div_clk - " "clk_set_rate failed\n", __func__); if (clk_set_rate(dsi_esc_clk, 2) < 0) /* divided by 2 */ pr_err("%s: dsi_esc_clk - " "clk_set_rate failed\n", __func__); mipi_dsi_pclk_ctrl(&dsi_pclk, 1); mipi_dsi_clk_ctrl(&dsicore_clk, 1); clk_enable(dsi_byte_div_clk); clk_enable(dsi_esc_clk); mdp4_stat.dsi_clk_on++; }
void mipi_dsi_clk_enable(void) { u32 pll_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0200); if (mipi_dsi_clk_on) { pr_info("%s: mipi_dsi_clks already ON\n", __func__); return; } MIPI_OUTP(MIPI_DSI_BASE + 0x0200, pll_ctrl | 0x01); mipi_dsi_phy_rdy_poll(); if (clk_set_rate(dsi_byte_div_clk, 1) < 0) /* divided by 1 */ pr_err("%s: dsi_byte_div_clk - " "clk_set_rate failed\n", __func__); if (clk_set_rate(dsi_esc_clk, esc_byte_ratio) < 0) /* divided by esc */ pr_err("%s: dsi_esc_clk - " /* clk ratio */ "clk_set_rate failed\n", __func__); mipi_dsi_pclk_ctrl(&dsi_pclk, 1); mipi_dsi_clk_ctrl(&dsicore_clk, 1); clk_enable(dsi_byte_div_clk); clk_enable(dsi_esc_clk); mipi_dsi_clk_on = 1; mdp4_stat.dsi_clk_on++; }
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info, int target_type) { struct mipi_dsi_phy_ctrl *pd; int i, off; MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */ msleep(100); MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */ MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */ MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */ MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */ MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */ MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */ pd = (panel_info->mipi).dsi_phy_db; off = 0x0480; /* strength 0 - 2 */ for (i = 0; i < 3; i++) { MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]); wmb(); off += 4; } off = 0x0470; /* ctrl 0 - 3 */ for (i = 0; i < 4; i++) { MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]); wmb(); off += 4; } off = 0x0500; /* regulator ctrl 0 - 4 */ for (i = 0; i < 5; i++) { MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]); wmb(); off += 4; } mipi_dsi_calibration(); off = 0x0204; /* pll ctrl 1 - 19, skip 0 */ for (i = 1; i < 20; i++) { MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]); wmb(); off += 4; } if (panel_info) mipi_dsi_phy_pll_config(panel_info->clk_rate); /* pll ctrl 0 */ MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]); wmb(); MIPI_OUTP(MIPI_DSI_BASE + 0x200, (pd->pll[0] | 0x01)); mipi_dsi_phy_rdy_poll(); off = 0x0440; /* phy timig ctrl 0 - 11 */ for (i = 0; i < 12; i++) { MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]); wmb(); off += 4; } clk_enable(dsi_byte_div_clk); clk_enable(dsi_esc_clk); if (target_type == 1) mipi_dsi_configure_serdes(); }