/* SH7372 specific MMCIF loader * * loads the zImage from an MMC card starting from block 1. * * The image must be start with a vrl4 header and * the zImage must start at offset 512 of the image. That is, * at block 2 (=byte 1024) on the media * * Use the following line to write the vrl4 formated zImage * to an MMC card * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 */ asmlinkage void mmc_loader(unsigned char *buf, unsigned long len) { mmc_init_progress(); mmc_update_progress(MMC_PROGRESS_ENTER); /* Initialise MMC * registers: PORT84CR-PORT92CR * (MMCD0_0-MMCD0_7,MMCCMD0 Control) * value: 0x04 - select function 4 */ __raw_writeb(0x04, PORT84CR); __raw_writeb(0x04, PORT85CR); __raw_writeb(0x04, PORT86CR); __raw_writeb(0x04, PORT87CR); __raw_writeb(0x04, PORT88CR); __raw_writeb(0x04, PORT89CR); __raw_writeb(0x04, PORT90CR); __raw_writeb(0x04, PORT91CR); __raw_writeb(0x04, PORT92CR); /* Initialise MMC * registers: PORT99CR (MMCCLK0 Control) * value: 0x10 | 0x04 - enable output | select function 4 */ __raw_writeb(0x14, PORT99CR); /* Enable clock to MMC hardware block */ __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_INIT); /* setup MMCIF hardware */ sh_mmcif_boot_init(MMCIF_BASE); mmc_update_progress(MMC_PROGRESS_LOAD); /* load kernel via MMCIF interface */ sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); /* Disable clock to MMC hardware block */ __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_DONE); }
asmlinkage void mmc_loader(unsigned short *buf, unsigned long len) { int high_capacity; mmc_init_progress(); mmc_update_progress(MMC_PROGRESS_ENTER); /* */ /* */ __raw_writeb(CR_FUNCTION1, PORT184CR); /* */ __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR); /* */ __raw_writeb(CR_FUNCTION1, PORT183CR); /* */ __raw_writeb(CR_FUNCTION1, PORT182CR); /* */ __raw_writeb(CR_FUNCTION1, PORT181CR); /* */ __raw_writeb(CR_FUNCTION1, PORT180CR); /* */ __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3); /* */ mmc_update_progress(MMC_PROGRESS_INIT); high_capacity = sdhi_boot_init(SDHI_BASE); if (high_capacity < 0) goto err; mmc_update_progress(MMC_PROGRESS_LOAD); /* */ if (sdhi_boot_do_read(SDHI_BASE, high_capacity, 0, /* */ (len + TMIO_BBS - 1) / TMIO_BBS, buf)) goto err; /* */ __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_DONE); return; err: for(;;); }
asmlinkage void mmc_loader(unsigned char *buf, unsigned long len) { mmc_init_progress(); mmc_update_progress(MMC_PROGRESS_ENTER); __raw_writeb(0x04, PORT84CR); __raw_writeb(0x04, PORT85CR); __raw_writeb(0x04, PORT86CR); __raw_writeb(0x04, PORT87CR); __raw_writeb(0x04, PORT88CR); __raw_writeb(0x04, PORT89CR); __raw_writeb(0x04, PORT90CR); __raw_writeb(0x04, PORT91CR); __raw_writeb(0x04, PORT92CR); __raw_writeb(0x14, PORT99CR); __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_INIT); sh_mmcif_boot_init(MMCIF_BASE); mmc_update_progress(MMC_PROGRESS_LOAD); sh_mmcif_boot_do_read(MMCIF_BASE, 2, (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3); mmc_update_progress(MMC_PROGRESS_DONE); }