/* Configures the global settings for the countes on all CPUs. */ static void fsl7450_reg_setup(struct op_counter_config *ctr, struct op_system_config *sys, int num_ctrs) { int i; /* Our counters count up, and "count" refers to * how much before the next interrupt, and we interrupt * on overflow. So we calculate the starting value * which will give us "count" until overflow. * Then we set the events on the enabled counters */ for (i = 0; i < NUM_CTRS; ++i) reset_value[i] = 0x80000000UL - ctr[i].count; /* Set events for Counters 1 & 2 */ mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event) | mmcr0_event2(ctr[1].event); /* Setup user/kernel bits */ if (sys->enable_kernel) mmcr0_val &= ~(MMCR0_FCS); if (sys->enable_user) mmcr0_val &= ~(MMCR0_FCP); /* Set events for Counters 3-6 */ mmcr1_val = mmcr1_event3(ctr[2].event) | mmcr1_event4(ctr[3].event) | mmcr1_event5(ctr[4].event) | mmcr1_event6(ctr[5].event); mmcr2_val = 0; }
static int fsl7450_reg_setup(struct op_counter_config *ctr, struct op_system_config *sys, int num_ctrs) { int i; num_pmcs = num_ctrs; /* */ for (i = 0; i < num_ctrs; ++i) reset_value[i] = 0x80000000UL - ctr[i].count; /* */ mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event) | mmcr0_event2(ctr[1].event); /* */ if (sys->enable_kernel) mmcr0_val &= ~(MMCR0_FCS); if (sys->enable_user) mmcr0_val &= ~(MMCR0_FCP); /* */ mmcr1_val = mmcr1_event3(ctr[2].event) | mmcr1_event4(ctr[3].event); if (num_ctrs > 4) mmcr1_val |= mmcr1_event5(ctr[4].event) | mmcr1_event6(ctr[5].event); mmcr2_val = 0; return 0; }