void enable_scu(unsigned long mpidr)
{
if (mpidr & MPIDR_CLUSTER_MASK)
mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg,
MP1_ACINACTM);
else
mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config,
MP0_ACINACTM);
}
void deassert_peripheral_reset(void)
{
mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
S10_RSTMGR_PER1MODRST_WATCHDOG0 |
S10_RSTMGR_PER1MODRST_WATCHDOG1 |
S10_RSTMGR_PER1MODRST_WATCHDOG2 |
S10_RSTMGR_PER1MODRST_WATCHDOG3 |
S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
S10_RSTMGR_PER1MODRST_SPTIMER0 |
S10_RSTMGR_PER1MODRST_SPTIMER1 |
S10_RSTMGR_PER1MODRST_I2C0 |
S10_RSTMGR_PER1MODRST_I2C1 |
S10_RSTMGR_PER1MODRST_I2C2 |
S10_RSTMGR_PER1MODRST_I2C3 |
S10_RSTMGR_PER1MODRST_I2C4 |
S10_RSTMGR_PER1MODRST_UART0 |
S10_RSTMGR_PER1MODRST_UART1 |
S10_RSTMGR_PER1MODRST_GPIO0 |
S10_RSTMGR_PER1MODRST_GPIO1);
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
S10_RSTMGR_PER0MODRST_EMAC0OCP |
S10_RSTMGR_PER0MODRST_EMAC1OCP |
S10_RSTMGR_PER0MODRST_EMAC2OCP |
S10_RSTMGR_PER0MODRST_USB0OCP |
S10_RSTMGR_PER0MODRST_USB1OCP |
S10_RSTMGR_PER0MODRST_NANDOCP |
S10_RSTMGR_PER0MODRST_SDMMCOCP |
S10_RSTMGR_PER0MODRST_DMAOCP);
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
S10_RSTMGR_PER0MODRST_EMAC0 |
S10_RSTMGR_PER0MODRST_EMAC1 |
S10_RSTMGR_PER0MODRST_EMAC2 |
S10_RSTMGR_PER0MODRST_USB0 |
S10_RSTMGR_PER0MODRST_USB1 |
S10_RSTMGR_PER0MODRST_NAND |
S10_RSTMGR_PER0MODRST_SDMMC |
S10_RSTMGR_PER0MODRST_DMA |
S10_RSTMGR_PER0MODRST_SPIM0 |
S10_RSTMGR_PER0MODRST_SPIM1 |
S10_RSTMGR_PER0MODRST_SPIS0 |
S10_RSTMGR_PER0MODRST_SPIS1 |
S10_RSTMGR_PER0MODRST_EMACPTP |
S10_RSTMGR_PER0MODRST_DMAIF0 |
S10_RSTMGR_PER0MODRST_DMAIF1 |
S10_RSTMGR_PER0MODRST_DMAIF2 |
S10_RSTMGR_PER0MODRST_DMAIF3 |
S10_RSTMGR_PER0MODRST_DMAIF4 |
S10_RSTMGR_PER0MODRST_DMAIF5 |
S10_RSTMGR_PER0MODRST_DMAIF6 |
S10_RSTMGR_PER0MODRST_DMAIF7);
}
void spm_boot_init(void)
{
/* set spm transaction to secure mode */
mmio_write_32(DEVAPC0_APC_CON, 0x0);
mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200);
/* Only CPU0 is online during boot, initialize cpu online reserve bit */
mmio_write_32(SPM_PCM_RESERVE, 0xFE);
mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF);
mmio_clrbits_32(AP_PLL_CON4, 0xF);
spm_lock_init();
spm_register_init();
}
static void mtcmos_ctrl_little_off(unsigned int linear_id)
{
uint32_t reg_pwr_con;
uint32_t reg_l1_pdn;
uint32_t bit_cpu;
switch (linear_id) {
case 1:
reg_pwr_con = SPM_CA7_CPU1_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU1_L1_PDN;
bit_cpu = LITTLE_CPU1;
break;
case 2:
reg_pwr_con = SPM_CA7_CPU2_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU2_L1_PDN;
bit_cpu = LITTLE_CPU2;
break;
case 3:
reg_pwr_con = SPM_CA7_CPU3_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU3_L1_PDN;
bit_cpu = LITTLE_CPU3;
break;
default:
/* should never come to here */
return;
}
/* enable register control */
mmio_write_32(SPM_POWERON_CONFIG_SET,
(SPM_PROJECT_CODE << 16) | (1U << 0));
mmio_setbits_32(reg_pwr_con, PWR_ISO);
mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
mmio_setbits_32(reg_l1_pdn, L1_PDN);
while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK))
continue;
mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
mmio_clrbits_32(reg_pwr_con, PWR_ON);
mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) ||
(mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu))
continue;
}
static int sys_pwr_domain_resume(void)
{
pmu_sgrf_rst_hld();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
plls_resume();
mmio_write_32(PMU_BASE + PMU_CCI500_CON,
WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) |
WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) |
WMSK_BIT(PMU_QGATING_CCI500_CFG));
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
WMSK_BIT(PMU_CLR_CORE_L_HW) |
WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) |
WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW));
mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON,
BIT(PMU_SCU_B_PWRDWN_EN));
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) |
WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW));
pmu_scu_b_pwrup();
plat_rockchip_gic_cpuif_enable();
return 0;
}
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
unsigned int con1;
con1 = mmio_read_32(SPM_PCM_CON1) &
~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
mmio_write_32(SPM_PCM_WDT_TIMER_VAL,
mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_PASR_DPD_0, 0);
mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff);
mmio_write_32(SPM_PCM_REG_DATA_INI, 0);
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags);
mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM,
(pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0));
mmio_write_32(SPM_PCM_PWR_IO_EN,
(pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) |
(pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0));
}
void mvebu_pmu_interrupt_enable(void)
{
unsigned int idx;
uint32_t flags;
int32_t rc;
/* Reset PIC */
mmio_write_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_MAX_IRQ_MASK);
/* Unmask PMU overflow IRQ in PIC0 */
mmio_clrbits_32(A7K8K_PIC0_MASK_REG, A7K8K_PIC_PMUOF_IRQ_MASK);
/* Configure ODMI Frame IRQs as edge triggered */
for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++)
gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx),
GIC_INTR_CFG_EDGE);
/*
* Register IRQ handler as INTR_TYPE_S_EL1 as its the only valid type
* for GICv2 in ARM-TF.
*/
flags = 0U;
set_interrupt_rm_flag((flags), (NON_SECURE));
rc = register_interrupt_type_handler(INTR_TYPE_S_EL1,
a7k8k_pmu_interrupt_handler,
flags);
if (rc != 0)
panic();
}
void soc_global_soft_reset_init(void)
{
mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
CRU_PMU_SGRF_RST_RLS);
mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON,
CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK);
}
static void hikey960_ufs_reset(void)
{
unsigned int data, mask;
mmio_write_32(CRG_PERDIS7_REG, 1 << 14);
mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN);
do {
data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG);
} while (data & BIT_SYSCTRL_REF_CLOCK_EN);
/* use abb clk */
mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1);
mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN);
mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16));
mdelay(1);
mmio_write_32(CRG_PEREN7_REG, 1 << 14);
mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN);
mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT);
do {
data = mmio_read_32(CRG_PERRSTSTAT3_REG);
} while ((data & PERI_UFS_BIT) == 0);
mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN);
mdelay(1);
mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY);
mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG,
MASK_UFS_DEVICE_RESET);
/* clear SC_DIV_UFS_PERIBUS */
mask = SC_DIV_UFS_PERIBUS << 16;
mmio_write_32(CRG_CLKDIV17_REG, mask);
/* set SC_DIV_UFSPHY_CFG(3) */
mask = SC_DIV_UFSPHY_CFG_MASK << 16;
data = SC_DIV_UFSPHY_CFG(3);
mmio_write_32(CRG_CLKDIV16_REG, mask | data);
data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG);
data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ;
data |= 0x39;
mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data);
mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL);
mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG,
MASK_UFS_CLK_GATE_BYPASS);
mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS);
mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN);
mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL);
mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL);
mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN);
mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT);
mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N);
mdelay(1);
mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG,
MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET);
mdelay(20);
mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG,
0x03300330);
mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT);
do {
data = mmio_read_32(CRG_PERRSTSTAT3_REG);
} while (data & PERI_UFS_BIT);
}
void hisi_clear_cpu_boot_flag(unsigned int cluster, unsigned int core)
{
unsigned int flag = BIT((cluster<<2) + core + 16);
hisi_cpuhotplug_lock(cluster, core);
mmio_clrbits_32(REG_SCBAKDATA3_OFFSET, flag);
hisi_cpuhotplug_unlock(cluster, core);
}
/*
* On boards without a proper PMIC we struggle to turn off the system properly.
* Try to turn off as much off the system as we can, to reduce power
* consumption. This should be entered with only one core running and SMP
* disabled.
* This function only cares about peripherals.
*/
void sunxi_turn_off_soc(uint16_t socid)
{
int i;
/** Turn off most peripherals, most importantly DRAM users. **/
/* Keep DRAM controller running for now. */
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
/* Contains msgbox (bit 21) and spinlock (bit 22) */
mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
/* Keep PIO controller running for now. */
mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
/* Contains UART0 (bit 16) */
mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
/** Turn off DRAM controller. **/
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
/** Migrate CPU and bus clocks away from the PLLs. **/
/* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
/* APB2: use OSC24M */
mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
/* AHB2: use AHB1 clock */
mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
/* CPU: use OSC24M */
mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
/** Turn off PLLs. **/
for (i = 0; i < 6; i++)
mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
switch (socid) {
case SUNXI_SOC_H5:
mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
break;
case SUNXI_SOC_A64:
mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
break;
}
}
void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power)
{
if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1)
&& ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) {
/* MCDI is offload? */
INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x",
__func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT),
mmio_read_32(SPM_CLK_CON));
return;
}
/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
* DISABLE_CPU_DROM */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
/* Wait SPM's response, can't use sleep api */
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK)
;
if (disable_dormant_power) {
mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR))
;
} else {
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR))
;
}
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event);
while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event)
;
/* Inform SPM to see updated setting */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE)
;
/* END OF sequence */
mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
}
void rk3399_flash_l2_b(void)
{
uint32_t wait_cnt = 0;
mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
dsb();
while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
BIT(L2_FLUSHDONE_CLUSTER_B))) {
wait_cnt++;
if (!(wait_cnt % MAX_WAIT_CONUT))
WARN("%s:reg %x,wait\n", __func__,
mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
}
mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
}
void spm_hotplug_off(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = platform_get_core_pos(mpidr);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK,
(1 << linear_id) |
(1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)));
spm_lock_release();
}
static void dma_end(void)
{
while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_TE_BIT) == 0) {
if ((mmio_read_32(DMA_DMACHCR) & DMACHCR_CHE_BIT) != 0U) {
ERROR("BL2: DMA - Channel Address Error\n");
panic();
break;
}
}
/* DMA transfer Disable */
mmio_clrbits_32(DMA_DMACHCR, DMACHCR_DE_BIT);
while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_DE_BIT) != 0)
;
mmio_write_32(DMA_DMASEC, 0);
mmio_write_16(DMA_DMAOR, 0);
mmio_write_32(DMA_DMACHCLR, DMA_USE_CHANNEL);
}
static void platform_setup_cpu(void)
{
/* setup big cores */
mmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res,
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS);
mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div,
MP1_SW_CG_GEN);
mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl,
MP1_L2RSTDISABLE);
/* set big cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg,
MP1_CPUCFG_64BIT);
/* set LITTLE cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw,
MP0_CPUCFG_64BIT);
}
static void sys_slp_config(void)
{
uint32_t slp_mode_cfg = 0;
mmio_write_32(PMU_BASE + PMU_CCI500_CON,
BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) |
BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) |
BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG));
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) |
BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) |
BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX,
BIT_WITH_WMSK(AP_PWROFF));
slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
BIT(PMU_POWER_OFF_REQ_CFG) |
BIT(PMU_CPU0_PD_EN) |
BIT(PMU_L2_FLUSH_EN) |
BIT(PMU_L2_IDLE_EN) |
BIT(PMU_SCU_PD_EN);
mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_CLUSTER_L_WKUP_EN);
mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_CLUSTER_B_WKUP_EN);
mmio_clrbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_GPIO_WKUP_EN);
mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(5));
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_MS(2));
}
static void platform_setup_cpu(void)
{
/* turn off all the little core's power except cpu 0 */
mtcmos_little_cpu_off();
/* setup big cores */
mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res,
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
MP1_SW_CG_GEN);
mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
MP1_L2RSTDISABLE);
/* set big cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
MP1_CPUCFG_64BIT);
/* set LITTLE cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
MP0_CPUCFG_64BIT);
/* enable dcm control */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN |
EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN |
INFRACLK_PSYS_DYNAMIC_CG_EN);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
L2C_SRAM_DCM_EN);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
MCU_BUS_DCM_EN);
}
static void hikey960_pmu_init(void)
{
/* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */
mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG);
}
static int stm32mp1_ddr_setup(void)
{
struct ddr_info *priv = &ddr_priv_data;
int ret;
struct stm32mp1_ddr_config config;
int node, len;
uint32_t uret, idx;
void *fdt;
#define PARAM(x, y) \
{ \
.name = x, \
.offset = offsetof(struct stm32mp1_ddr_config, y), \
.size = sizeof(config.y) / sizeof(uint32_t) \
}
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
const struct {
const char *name; /* Name in DT */
const uint32_t offset; /* Offset in config struct */
const uint32_t size; /* Size of parameters */
} param[] = {
CTL_PARAM(reg),
CTL_PARAM(timing),
CTL_PARAM(map),
CTL_PARAM(perf),
PHY_PARAM(reg),
PHY_PARAM(timing),
PHY_PARAM(cal)
};
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
ERROR("%s: Cannot read DDR node in DT\n", __func__);
return -EINVAL;
}
config.info.speed = fdt_read_uint32_default(node, "st,mem-speed", 0);
if (!config.info.speed) {
VERBOSE("%s: no st,mem-speed\n", __func__);
return -EINVAL;
}
config.info.size = fdt_read_uint32_default(node, "st,mem-size", 0);
if (!config.info.size) {
VERBOSE("%s: no st,mem-size\n", __func__);
return -EINVAL;
}
config.info.name = fdt_getprop(fdt, node, "st,mem-name", &len);
if (config.info.name == NULL) {
VERBOSE("%s: no st,mem-name\n", __func__);
return -EINVAL;
}
INFO("RAM: %s\n", config.info.name);
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
ret = fdt_read_uint32_array(node, param[idx].name,
(void *)((uintptr_t)&config +
param[idx].offset),
param[idx].size);
VERBOSE("%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
if (ret != 0) {
ERROR("%s: Cannot read %s\n",
__func__, param[idx].name);
return -EINVAL;
}
}
/* Disable axidcg clock gating during init */
mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
stm32mp1_ddr_init(priv, &config);
/* Enable axidcg clock gating */
mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
priv->info.size = config.info.size;
VERBOSE("%s : ram size(%x, %x)\n", __func__,
(uint32_t)priv->info.base, (uint32_t)priv->info.size);
write_sctlr(read_sctlr() & ~SCTLR_C_BIT);
dcsw_op_all(DC_OP_CISW);
uret = ddr_test_data_bus();
if (uret != 0U) {
ERROR("DDR data bus test: can't access memory @ 0x%x\n",
uret);
panic();
}
uret = ddr_test_addr_bus();
if (uret != 0U) {
ERROR("DDR addr bus test: can't access memory @ 0x%x\n",
uret);
panic();
}
uret = ddr_check_size();
if (uret < config.info.size) {
ERROR("DDR size: 0x%x does not match DT config: 0x%x\n",
uret, config.info.size);
panic();
}
write_sctlr(read_sctlr() | SCTLR_C_BIT);
return 0;
}
void hisi_clear_cpuidle_flag(unsigned int cluster, unsigned int core)
{
mmio_clrbits_32(CPUIDLE_FLAG_REG(cluster), BIT(core));
}
static void pmu_scu_b_pwrup(void)
{
mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
}
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
{
uint32_t flags_cmd, status;
uint32_t flags_data = 0;
int err = 0;
uintptr_t base = sdmmc2_params.reg_base;
unsigned int cmd_reg, arg_reg, start;
if (cmd == NULL) {
return -EINVAL;
}
flags_cmd = SDMMC_STAR_CTIMEOUT;
arg_reg = cmd->cmd_arg;
if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
mmio_write_32(base + SDMMC_CMDR, 0);
}
cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN;
if (cmd->resp_type == 0U) {
flags_cmd |= SDMMC_STAR_CMDSENT;
}
if ((cmd->resp_type & MMC_RSP_48) != 0U) {
if ((cmd->resp_type & MMC_RSP_136) != 0U) {
flags_cmd |= SDMMC_STAR_CMDREND;
cmd_reg |= SDMMC_CMDR_WAITRESP;
} else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) {
flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL;
cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT;
} else {
flags_cmd |= SDMMC_STAR_CMDREND;
cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC;
}
}
switch (cmd->cmd_idx) {
case MMC_CMD(1):
arg_reg |= OCR_POWERUP;
break;
case MMC_CMD(8):
if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
cmd_reg |= SDMMC_CMDR_CMDTRANS;
}
break;
case MMC_CMD(12):
cmd_reg |= SDMMC_CMDR_CMDSTOP;
break;
case MMC_CMD(17):
case MMC_CMD(18):
cmd_reg |= SDMMC_CMDR_CMDTRANS;
if (sdmmc2_params.use_dma) {
flags_data |= SDMMC_STAR_DCRCFAIL |
SDMMC_STAR_DTIMEOUT |
SDMMC_STAR_DATAEND |
SDMMC_STAR_RXOVERR |
SDMMC_STAR_IDMATE;
}
break;
case MMC_ACMD(41):
arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4;
break;
case MMC_ACMD(51):
cmd_reg |= SDMMC_CMDR_CMDTRANS;
if (sdmmc2_params.use_dma) {
flags_data |= SDMMC_STAR_DCRCFAIL |
SDMMC_STAR_DTIMEOUT |
SDMMC_STAR_DATAEND |
SDMMC_STAR_RXOVERR |
SDMMC_STAR_IDMATE |
SDMMC_STAR_DBCKEND;
}
break;
default:
break;
}
if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
}
mmio_write_32(base + SDMMC_ARGR, arg_reg);
mmio_write_32(base + SDMMC_CMDR, cmd_reg);
status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0);
while ((status & flags_cmd) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) {
err = -ETIMEDOUT;
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
goto err_exit;
}
status = mmio_read_32(base + SDMMC_STAR);
}
if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) {
if ((status & SDMMC_STAR_CTIMEOUT) != 0U) {
err = -ETIMEDOUT;
/*
* Those timeouts can occur, and framework will handle
* the retries. CMD8 is expected to return this timeout
* for eMMC
*/
if (!((cmd->cmd_idx == MMC_CMD(1)) ||
(cmd->cmd_idx == MMC_CMD(13)) ||
((cmd->cmd_idx == MMC_CMD(8)) &&
(cmd->resp_type == MMC_RESPONSE_R7)))) {
ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
}
} else {
err = -EIO;
ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
}
goto err_exit;
}
if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) {
if ((cmd->cmd_idx == MMC_CMD(9)) &&
((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) {
/* Need to invert response to match CSD structure */
cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
} else {
cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
if ((cmd_reg & SDMMC_CMDR_WAITRESP) ==
SDMMC_CMDR_WAITRESP) {
cmd->resp_data[1] = mmio_read_32(base +
SDMMC_RESP2R);
cmd->resp_data[2] = mmio_read_32(base +
SDMMC_RESP3R);
cmd->resp_data[3] = mmio_read_32(base +
SDMMC_RESP4R);
}
}
}
if (flags_data == 0U) {
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
return 0;
}
status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0);
while ((status & flags_data) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) {
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
err = -ETIMEDOUT;
goto err_exit;
}
status = mmio_read_32(base + SDMMC_STAR);
};
if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
SDMMC_STAR_IDMATE)) != 0U) {
ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__,
cmd->cmd_idx, status);
err = -EIO;
}
err_exit:
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
if (err != 0) {
int ret_stop = stm32_sdmmc2_stop_transfer();
if (ret_stop != 0) {
return ret_stop;
}
}
return err;
}