void spm_clean_after_wakeup(void)
{
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0);
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY);
mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C);
mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF);
}
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
unsigned int con1;
con1 = mmio_read_32(SPM_PCM_CON1) &
~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
mmio_write_32(SPM_PCM_WDT_TIMER_VAL,
mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_PASR_DPD_0, 0);
mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff);
mmio_write_32(SPM_PCM_REG_DATA_INI, 0);
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags);
mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM,
(pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0));
mmio_write_32(SPM_PCM_PWR_IO_EN,
(pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) |
(pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0));
}
int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
stm32mp_clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_ITF_SHIFT);
stm32mp_clk_disable(RTCAPB);
return 0;
}
void spm_hotplug_off(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = platform_get_core_pos(mpidr);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK,
(1 << linear_id) |
(1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)));
spm_lock_release();
}
void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) |
(!pwrctrl->mfg_req_mask << 17) |
(!pwrctrl->disp_req_mask << 16) |
(!!pwrctrl->mcusys_idle_mask << 7) |
(!!pwrctrl->ca15top_idle_mask << 6) |
(!!pwrctrl->ca7top_idle_mask << 5) |
(!!pwrctrl->wfi_op << 4));
mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0));
mmio_write_32(SPM_PCM_PASR_DPD_2, 0);
mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0,
(pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0));
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en);
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en);
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en);
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en);
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en);
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en);
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en);
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en);
}
static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
{
struct mmc_cmd cmd;
int ret;
uintptr_t base = sdmmc2_params.reg_base;
uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
if (size == 8U) {
data_ctrl |= SDMMC_DBLOCKSIZE_8;
} else {
data_ctrl |= SDMMC_DBLOCKSIZE_512;
}
sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
if (sdmmc2_params.use_dma) {
inv_dcache_range(buf, size);
}
/* Prepare CMD 16*/
mmio_write_32(base + SDMMC_DTIMER, 0);
mmio_write_32(base + SDMMC_DLENR, 0);
mmio_write_32(base + SDMMC_DCTRLR, 0);
zeromem(&cmd, sizeof(struct mmc_cmd));
cmd.cmd_idx = MMC_CMD(16);
if (size > MMC_BLOCK_SIZE) {
cmd.cmd_arg = MMC_BLOCK_SIZE;
} else {
cmd.cmd_arg = size;
}
cmd.resp_type = MMC_RESPONSE_R1;
ret = stm32_sdmmc2_send_cmd(&cmd);
if (ret != 0) {
ERROR("CMD16 failed\n");
return ret;
}
/* Prepare data command */
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
mmio_write_32(base + SDMMC_DLENR, size);
if (sdmmc2_params.use_dma) {
mmio_write_32(base + SDMMC_IDMACTRLR,
SDMMC_IDMACTRLR_IDMAEN);
mmio_write_32(base + SDMMC_IDMABASE0R, buf);
flush_dcache_range(buf, size);
}
mmio_clrsetbits_32(base + SDMMC_DCTRLR,
SDMMC_DCTRLR_CLEAR_MASK,
data_ctrl);
return 0;
}
