uint16_t _cpu_fetch(cpu_t *cpu, mmu_abort_t *abort)
{
uint16_t insnWord = mmu_read_word(cpu->mmu, cpu->r[7], abort);
printf("_cpu_fetch: fetched %06o\n", insnWord);
return insnWord;
}
static void
mac_write (struct device_desc *dev)
{
struct device_interrupt *intr = &dev->intr;
struct net_device *net_dev = (struct net_device *) dev->dev;
struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data;
struct machine_config *mc = (struct machine_config *) dev->mach;
ARMul_State *state = (ARMul_State *) mc->state;
fault_t fault;
u32 ptr, status, len;
int i;
fault = mmu_read_word (state, io->bdmatxptr, &ptr);
/*
if( fault ) {
*addr = io->bdmatxptr;
return fault;
}
*/
if (!(ptr & BDMA_owner))
return;
ptr &= ~BDMA_owner;
fault = mmu_read_word (state, io->bdmatxptr + 8, &len);
/*
if( fault ) {
*addr = io->bdmatxptr + 8;
return fault;
}
*/
len &= 0xffff;
if (len > sizeof (io->mac_buf))
return;
for (i = 0; i < len; i++) {
fault = mmu_read_byte (state, ptr + i, io->mac_buf + i);
/*
if( fault ) {
*addr = ptr + i;
return fault;
}
*/
}
//Update TXstatus
status = len | (Comp << 16);
fault = mmu_write_word (state, io->bdmatxptr + 8, status);
//print_packet(io->mac_buf, len);
/*
if( fault ) {
*addr = io->bdmatxptr + 8;
return fault;
}
*/
//set owner bit of desc to CPU
fault = mmu_write_word (state, io->bdmatxptr, ptr);
/*
if( fault ) {
*addr = io->bdmatxptr;
return fault;
}
*/
//get next desc
fault = mmu_read_word (state, io->bdmatxptr + 12, &io->bdmatxptr);
/*
if( fault ) {
*addr = io->bdmatxptr + 12;
*/
net_dev->net_write (net_dev, io->mac_buf, len);
//write( skyeye_config.net[0].fd, io->mac_buf, len );
//trigger interrupt
if (io->mactxcon & EnComp) {
mc->mach_set_intr (intr->interrupts[INT_S3C4510B_MACTX]);
mc->mach_update_intr (mc);
//s3c4510b_set_interrupt(INT_MACTX);
//s3c4510b_update_int(state);
}
}
static void
mac_read (struct device_desc *dev)
{
struct device_interrupt *intr = &dev->intr;
struct net_device *net_dev = (struct net_device *) dev->dev;
struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data;
struct machine_config *mc = (struct machine_config *) dev->mach;
ARMul_State *state = (ARMul_State *) mc->state;
int packet_len, s3c4510b_len;
fault_t fault;
u32 ptr, status_len;
int n, i;
//*addr = 0;
packet_len =
net_dev->net_read (net_dev, io->mac_buf,
sizeof (io->mac_buf));
//n = read(skyeye_config.net[0].fd, mac_buf, sizeof(mac_buf));
if (packet_len <= 0)
return;
fault = mmu_read_word (state, io->bdmarxptr, &ptr);
//print_packet(io->mac_buf, packet_len);
/*
if( fault ) {
*addr = io->bdmarxptr;
return fault;
}
*/
if (!(ptr & BDMA_owner))
return;
ptr &= ~BDMA_owner;
//if( len + 2 > sizeof(mac_buf) ) return 0;
/* FIXME:for s3c4510b frame, ptr offset is 2 */
for (i = 0; i < packet_len; i++) {
fault = mmu_write_byte (state, ptr + 2 + i,
*(io->mac_buf + i));
/*
if(fault) {
*addr = ptr + 2 + i;
return fault;
}
*/
}
//in desc, set Good bit for RX status , and set len
status_len = (Good << 16) | (packet_len + 4);
//printf("status_len:%x\n",status_len);
fault = mmu_write_word (state, io->bdmarxptr + 8, status_len);
/*
if(fault) {
*addr = io->bdmarxptr+8;
return fault;
}
*/
//set owner bit of desc to CPU
fault = mmu_write_word (state, io->bdmarxptr, ptr);
/*
if(fault) {
*addr = io->bdmarxptr;
return fault;
}
*/
//get next desc
fault = mmu_read_word (state, io->bdmarxptr + 12, &io->bdmarxptr);
/*
if(fault) {
*addr = io->bdmarxptr + 12;
return fault;
}
*/
/* update bdmastat register */
io->bdmastat |= S_BRxRDF;
mc->mach_set_intr (intr->interrupts[INT_S3C4510B_BDMARX]);
mc->mach_update_intr (mc);
}
