static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { int cpu = cpu_logical_map(0); scu_enable(scu_base); /* enable cache coherency on CPU0 */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); }
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { cpu = cpu_logical_map(cpu); /* enable cache coherency */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); gic_raise_softirq(cpumask_of(cpu), 1); return 0; }
int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; int ret = -EIO; cpu = cpu_logical_map(cpu); /* disable cache coherency */ modify_scu_cpu_psr(3 << (cpu * 8), 0); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; if (ch) ret = r8a7779_sysc_power_down(ch); return ret ? ret : 1; }
int __cpuinit r8a7779_boot_secondary(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; int ret = -EIO; cpu = cpu_logical_map(cpu); /* enable cache coherency */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; if (ch) ret = r8a7779_sysc_power_up(ch); return ret; }
void __init r8a7779_smp_prepare_cpus(void) { int cpu = cpu_logical_map(0); scu_enable(scu_base_addr()); /* Map the reset vector (in headsmp.S) */ __raw_writel(__pa(shmobile_secondary_vector), AVECR); /* enable cache coherency on CPU0 */ modify_scu_cpu_psr(0, 3 << (cpu * 8)); r8a7779_pm_init(); /* power off secondary CPUs */ r8a7779_platform_cpu_kill(1); r8a7779_platform_cpu_kill(2); r8a7779_platform_cpu_kill(3); }