void gensllv(void) { #if defined(COUNT_INSTR) inc_m32abs(&instr_count[58]); #endif #ifdef INTERPRET_SLLV gencallinterp((unsigned long long)SLLV, 0); #else int rt, rd; allocate_register_32_manually(ECX, (unsigned int *)dst->f.r.rs); rt = allocate_register_32((unsigned int *)dst->f.r.rt); rd = allocate_register_32_w((unsigned int *)dst->f.r.rd); if (rd != ECX) { mov_reg32_reg32(rd, rt); shl_reg32_cl(rd); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rt); shl_reg32_cl(temp); mov_reg32_reg32(rd, temp); } #endif }
void gensllv(usf_state_t * state) { #ifdef INTERPRET_SLLV gencallinterp(state, (unsigned int)state->current_instruction_table.SLLV, 0); #else int rt, rd; allocate_register_manually(state, ECX, (unsigned int *)state->dst->f.r.rs); rt = allocate_register(state, (unsigned int *)state->dst->f.r.rt); rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd); if (rd != ECX) { mov_reg32_reg32(state, rd, rt); shl_reg32_cl(state, rd); } else { int temp = lru_register(state); free_register(state, temp); mov_reg32_reg32(state, temp, rt); shl_reg32_cl(state, temp); mov_reg32_reg32(state, rd, temp); } #endif }
void gensrav(void) { #ifdef INTERPRET_SRAV gencallinterp((unsigned int)cached_interpreter_table.SRAV, 0); #else int rt, rd; allocate_register_manually(ECX, (unsigned int *)dst->f.r.rs); rt = allocate_register((unsigned int *)dst->f.r.rt); rd = allocate_register_w((unsigned int *)dst->f.r.rd); if (rd != ECX) { mov_reg32_reg32(rd, rt); sar_reg32_cl(rd); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rt); sar_reg32_cl(temp); mov_reg32_reg32(rd, temp); } #endif }
void gensrav(void) { #if defined(COUNT_INSTR) inc_m32rel(&instr_count[60]); #endif #ifdef INTERPRET_SRAV gencallinterp((unsigned long long)cached_interpreter_table.SRAV, 0); #else int rt, rd; allocate_register_32_manually(ECX, (unsigned int *)dst->f.r.rs); rt = allocate_register_32((unsigned int *)dst->f.r.rt); rd = allocate_register_32_w((unsigned int *)dst->f.r.rd); if (rd != ECX) { mov_reg32_reg32(rd, rt); sar_reg32_cl(rd); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rt); sar_reg32_cl(temp); mov_reg32_reg32(rd, temp); } #endif }
void gensllv() { #ifdef INTERPRET_SLLV gencallinterp((unsigned long)SLLV, 0); #else int rt, rd; allocate_register_manually(ECX, (unsigned long *)dst->f.r.rs); rt = allocate_register((unsigned long *)dst->f.r.rt); rd = allocate_register_w((unsigned long *)dst->f.r.rd); if (rd != ECX) { mov_reg32_reg32(rd, rt); shl_reg32_cl(rd); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rt); shl_reg32_cl(temp); mov_reg32_reg32(rd, temp); } #endif }
void genmtlo(usf_state_t * state) { #ifdef INTERPRET_MTLO gencallinterp(state, (unsigned int)state->current_instruction_table.MTLO, 0); #else int lo1 = allocate_64_register1_w(state, (unsigned int*)&state->lo); int lo2 = allocate_64_register2_w(state, (unsigned int*)&state->lo); int rs1 = allocate_64_register1(state, (unsigned int*)state->dst->f.r.rs); int rs2 = allocate_64_register2(state, (unsigned int*)state->dst->f.r.rs); mov_reg32_reg32(state, lo1, rs1); mov_reg32_reg32(state, lo2, rs2); #endif }
void genmfhi(usf_state_t * state) { #ifdef INTERPRET_MFHI gencallinterp(state, (unsigned int)state->current_instruction_table.MFHI, 0); #else int rd1 = allocate_64_register1_w(state, (unsigned int*)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int*)state->dst->f.r.rd); int hi1 = allocate_64_register1(state, (unsigned int*)&state->hi); int hi2 = allocate_64_register2(state, (unsigned int*)&state->hi); mov_reg32_reg32(state, rd1, hi1); mov_reg32_reg32(state, rd2, hi2); #endif }
void genmtlo() { #ifdef INTERPRET_MTLO gencallinterp((unsigned long)MTLO, 0); #else int lo1 = allocate_64_register1_w((unsigned long*)&lo); int lo2 = allocate_64_register2_w((unsigned long*)&lo); int rs1 = allocate_64_register1((unsigned long*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long*)dst->f.r.rs); mov_reg32_reg32(lo1, rs1); mov_reg32_reg32(lo2, rs2); #endif }
void genmfhi() { #ifdef INTERPRET_MFHI gencallinterp((unsigned long)MFHI, 0); #else int rd1 = allocate_64_register1_w((unsigned long*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long*)dst->f.r.rd); int hi1 = allocate_64_register1((unsigned long*)&hi); int hi2 = allocate_64_register2((unsigned long*)&hi); mov_reg32_reg32(rd1, hi1); mov_reg32_reg32(rd2, hi2); #endif }
void genmfhi(void) { #ifdef INTERPRET_MFHI gencallinterp((unsigned int)cached_interpreter_table.MFHI, 0); #else int rd1 = allocate_64_register1_w((unsigned int*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int*)dst->f.r.rd); int hi1 = allocate_64_register1((unsigned int*)&hi); int hi2 = allocate_64_register2((unsigned int*)&hi); mov_reg32_reg32(rd1, hi1); mov_reg32_reg32(rd2, hi2); #endif }
void genmflo(void) { #ifdef INTERPRET_MFLO gencallinterp((unsigned int)cached_interpreter_table.MFLO, 0); #else int rd1 = allocate_64_register1_w((unsigned int*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int*)dst->f.r.rd); int lo1 = allocate_64_register1((unsigned int*)&lo); int lo2 = allocate_64_register2((unsigned int*)&lo); mov_reg32_reg32(rd1, lo1); mov_reg32_reg32(rd2, lo2); #endif }
void genmflo() { #ifdef INTERPRET_MFLO gencallinterp((unsigned long)MFLO, 0); #else int rd1 = allocate_64_register1_w((unsigned long*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long*)dst->f.r.rd); int lo1 = allocate_64_register1((unsigned long*)&lo); int lo2 = allocate_64_register2((unsigned long*)&lo); mov_reg32_reg32(rd1, lo1); mov_reg32_reg32(rd2, lo2); #endif }
void genmtlo(void) { #ifdef INTERPRET_MTLO gencallinterp((unsigned int)cached_interpreter_table.MTLO, 0); #else int lo1 = allocate_64_register1_w((unsigned int*)&lo); int lo2 = allocate_64_register2_w((unsigned int*)&lo); int rs1 = allocate_64_register1((unsigned int*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int*)dst->f.r.rs); mov_reg32_reg32(lo1, rs1); mov_reg32_reg32(lo2, rs2); #endif }
void genmthi() { #ifdef INTERPRET_MTHI gencallinterp((unsigned long)MTHI, 0); #else int hi1 = allocate_64_register1_w((unsigned long*)&hi); int hi2 = allocate_64_register2_w((unsigned long*)&hi); int rs1 = allocate_64_register1((unsigned long*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long*)dst->f.r.rs); mov_reg32_reg32(hi1, rs1); mov_reg32_reg32(hi2, rs2); #endif }
void genmthi(void) { #ifdef INTERPRET_MTHI gencallinterp((unsigned int)cached_interpreter_table.MTHI, 0); #else int hi1 = allocate_64_register1_w((unsigned int*)&hi); int hi2 = allocate_64_register2_w((unsigned int*)&hi); int rs1 = allocate_64_register1((unsigned int*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int*)dst->f.r.rs); mov_reg32_reg32(hi1, rs1); mov_reg32_reg32(hi2, rs2); #endif }
void gensubu(void) { #if defined(COUNT_INSTR) inc_m32abs(&instr_count[82]); #endif #ifdef INTERPRET_SUBU gencallinterp((unsigned long long)SUBU, 0); #else int rs = allocate_register_32((unsigned int *)dst->f.r.rs); int rt = allocate_register_32((unsigned int *)dst->f.r.rt); int rd = allocate_register_32_w((unsigned int *)dst->f.r.rd); if (rs == rd) sub_reg32_reg32(rd, rt); else if (rt == rd) { neg_reg32(rd); add_reg32_reg32(rd, rs); } else { mov_reg32_reg32(rd, rs); sub_reg32_reg32(rd, rt); } #endif }
void gendsrl(void) { #ifdef INTERPRET_DSRL gencallinterp((unsigned int)cached_interpreter_table.DSRL, 0); #else int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); shr_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); xor_reg32_reg32(rd2, rd2); } #endif }
void gendsra32() { #ifdef INTERPRET_DSRA32 gencallinterp((unsigned long)DSRA32, 0); #else int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd = allocate_register_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd, rt2); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
void gendsra() { #ifdef INTERPRET_DSRA gencallinterp((unsigned long)DSRA, 0); #else int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); sar_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); sar_reg32_imm8(rd2, 31); } #endif }
void gensra(void) { #ifdef INTERPRET_SRA gencallinterp((unsigned int)cached_interpreter_table.SRA, 0); #else int rt = allocate_register((unsigned int *)dst->f.r.rt); int rd = allocate_register_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd, rt); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
void gensrl(void) { #ifdef INTERPRET_SRL gencallinterp((unsigned int)cached_interpreter_table.SRL, 0); #else int rt = allocate_register((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd = allocate_register_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); mov_reg32_reg32(rd, rt); shr_reg32_imm8(rd, g_dev.r4300.recomp.dst->f.r.sa); #endif }
void gendsra(usf_state_t * state) { #ifdef INTERPRET_DSRA gencallinterp(state, (unsigned int)state->current_instruction_table.DSRA, 0); #else int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); mov_reg32_reg32(state, rd1, rt1); mov_reg32_reg32(state, rd2, rt2); shrd_reg32_reg32_imm8(state, rd1, rd2, state->dst->f.r.sa); sar_reg32_imm8(state, rd2, state->dst->f.r.sa); if (state->dst->f.r.sa & 0x20) { mov_reg32_reg32(state, rd1, rd2); sar_reg32_imm8(state, rd2, 31); } #endif }
void gendsra32(void) { #ifdef INTERPRET_DSRA32 gencallinterp((unsigned int)cached_interpreter_table.DSRA32, 0); #else int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd = allocate_register_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd, rt2); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
void gensra(usf_state_t * state) { #ifdef INTERPRET_SRA gencallinterp(state, (unsigned int)state->current_instruction_table.SRA, 0); #else int rt = allocate_register(state, (unsigned int *)state->dst->f.r.rt); int rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd); mov_reg32_reg32(state, rd, rt); sar_reg32_imm8(state, rd, state->dst->f.r.sa); #endif }
void gendsra(void) { #ifdef INTERPRET_DSRA gencallinterp((unsigned int)cached_interpreter_table.DSRA, 0); #else int rt1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, g_dev.r4300.recomp.dst->f.r.sa); sar_reg32_imm8(rd2, g_dev.r4300.recomp.dst->f.r.sa); if (g_dev.r4300.recomp.dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); sar_reg32_imm8(rd2, 31); } #endif }
void gensra() { #ifdef INTERPRET_SRA gencallinterp((unsigned long)SRA, 0); #else int rt = allocate_register((unsigned long *)dst->f.r.rt); int rd = allocate_register_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd, rt); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
void gendsub() { #ifdef INTERPRET_DSUB gencallinterp((unsigned long)DSUB, 0); #else int rs1 = allocate_64_register1((unsigned long *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); sub_reg32_reg32(rd1, rt1); sbb_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); sub_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); sbb_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }
void gendsub(void) { #ifdef INTERPRET_DSUB gencallinterp((unsigned int)cached_interpreter_table.DSUB, 0); #else int rs1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); int rt1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); sub_reg32_reg32(rd1, rt1); sbb_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); sub_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); sbb_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }
void gendsub(usf_state_t * state) { #ifdef INTERPRET_DSUB gencallinterp(state, (unsigned int)state->current_instruction_table.DSUB, 0); #else int rs1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rs); int rs2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rs); int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(state, rd1, rs1); mov_reg32_reg32(state, rd2, rs2); sub_reg32_reg32(state, rd1, rt1); sbb_reg32_reg32(state, rd2, rt2); } else { int temp = lru_register(state); free_register(state, temp); mov_reg32_reg32(state, temp, rs1); sub_reg32_reg32(state, temp, rt1); mov_reg32_reg32(state, rd1, temp); mov_reg32_reg32(state, temp, rs2); sbb_reg32_reg32(state, temp, rt2); mov_reg32_reg32(state, rd2, temp); } #endif }
void gendaddu(void) { #ifdef INTERPRET_DADDU gencallinterp((unsigned int)cached_interpreter_table.DADDU, 0); #else int rs1 = allocate_64_register1((unsigned int *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); add_reg32_reg32(rd1, rt1); adc_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); add_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); adc_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }